-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024
-- Date        : Thu Nov  6 20:01:06 2025
-- Host        : DESKTOP-IL2I0O0 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               d:/programs/FPGA/multi_lia_pipline_ds/multi_lia_pipline_ds.gen/sources_1/ip/IIR_2_core_pipline_0/IIR_2_core_pipline_0_sim_netlist.vhdl
-- Design      : IIR_2_core_pipline_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tfgg484-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity IIR_2_core_pipline_0_IIR_single_stage_dsp is
  port (
    Xin : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Xin1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Xin2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Yin1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Yin2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Yout : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is "IIR_single_stage_dsp";
  attribute a0 : integer;
  attribute a0 of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is 131072;
  attribute a1 : integer;
  attribute a1 of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is -186275;
  attribute a2 : integer;
  attribute a2 of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is 67915;
  attribute b0 : integer;
  attribute b0 of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is 1636;
  attribute b1 : integer;
  attribute b1 of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is -531;
  attribute b2 : integer;
  attribute b2 of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is 1636;
  attribute coeffct_width : integer;
  attribute coeffct_width of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is 20;
  attribute daout_width : integer;
  attribute daout_width of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is 16;
  attribute datin_width : integer;
  attribute datin_width of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is 16;
  attribute dont_touch : string;
  attribute dont_touch of IIR_2_core_pipline_0_IIR_single_stage_dsp : entity is "true";
end IIR_2_core_pipline_0_IIR_single_stage_dsp;

architecture STRUCTURE of IIR_2_core_pipline_0_IIR_single_stage_dsp is
  signal XMult2_n_10 : STD_LOGIC;
  signal XMult2_n_100 : STD_LOGIC;
  signal XMult2_n_101 : STD_LOGIC;
  signal XMult2_n_102 : STD_LOGIC;
  signal XMult2_n_103 : STD_LOGIC;
  signal XMult2_n_104 : STD_LOGIC;
  signal XMult2_n_105 : STD_LOGIC;
  signal XMult2_n_106 : STD_LOGIC;
  signal XMult2_n_107 : STD_LOGIC;
  signal XMult2_n_108 : STD_LOGIC;
  signal XMult2_n_109 : STD_LOGIC;
  signal XMult2_n_11 : STD_LOGIC;
  signal XMult2_n_110 : STD_LOGIC;
  signal XMult2_n_111 : STD_LOGIC;
  signal XMult2_n_112 : STD_LOGIC;
  signal XMult2_n_113 : STD_LOGIC;
  signal XMult2_n_114 : STD_LOGIC;
  signal XMult2_n_115 : STD_LOGIC;
  signal XMult2_n_116 : STD_LOGIC;
  signal XMult2_n_117 : STD_LOGIC;
  signal XMult2_n_118 : STD_LOGIC;
  signal XMult2_n_119 : STD_LOGIC;
  signal XMult2_n_12 : STD_LOGIC;
  signal XMult2_n_120 : STD_LOGIC;
  signal XMult2_n_121 : STD_LOGIC;
  signal XMult2_n_122 : STD_LOGIC;
  signal XMult2_n_123 : STD_LOGIC;
  signal XMult2_n_124 : STD_LOGIC;
  signal XMult2_n_125 : STD_LOGIC;
  signal XMult2_n_126 : STD_LOGIC;
  signal XMult2_n_127 : STD_LOGIC;
  signal XMult2_n_128 : STD_LOGIC;
  signal XMult2_n_129 : STD_LOGIC;
  signal XMult2_n_13 : STD_LOGIC;
  signal XMult2_n_130 : STD_LOGIC;
  signal XMult2_n_131 : STD_LOGIC;
  signal XMult2_n_132 : STD_LOGIC;
  signal XMult2_n_133 : STD_LOGIC;
  signal XMult2_n_134 : STD_LOGIC;
  signal XMult2_n_135 : STD_LOGIC;
  signal XMult2_n_136 : STD_LOGIC;
  signal XMult2_n_137 : STD_LOGIC;
  signal XMult2_n_138 : STD_LOGIC;
  signal XMult2_n_139 : STD_LOGIC;
  signal XMult2_n_14 : STD_LOGIC;
  signal XMult2_n_140 : STD_LOGIC;
  signal XMult2_n_141 : STD_LOGIC;
  signal XMult2_n_142 : STD_LOGIC;
  signal XMult2_n_143 : STD_LOGIC;
  signal XMult2_n_144 : STD_LOGIC;
  signal XMult2_n_145 : STD_LOGIC;
  signal XMult2_n_146 : STD_LOGIC;
  signal XMult2_n_147 : STD_LOGIC;
  signal XMult2_n_148 : STD_LOGIC;
  signal XMult2_n_149 : STD_LOGIC;
  signal XMult2_n_15 : STD_LOGIC;
  signal XMult2_n_150 : STD_LOGIC;
  signal XMult2_n_151 : STD_LOGIC;
  signal XMult2_n_152 : STD_LOGIC;
  signal XMult2_n_153 : STD_LOGIC;
  signal XMult2_n_16 : STD_LOGIC;
  signal XMult2_n_17 : STD_LOGIC;
  signal XMult2_n_18 : STD_LOGIC;
  signal XMult2_n_19 : STD_LOGIC;
  signal XMult2_n_20 : STD_LOGIC;
  signal XMult2_n_21 : STD_LOGIC;
  signal XMult2_n_22 : STD_LOGIC;
  signal XMult2_n_23 : STD_LOGIC;
  signal XMult2_n_6 : STD_LOGIC;
  signal XMult2_n_7 : STD_LOGIC;
  signal XMult2_n_78 : STD_LOGIC;
  signal XMult2_n_79 : STD_LOGIC;
  signal XMult2_n_8 : STD_LOGIC;
  signal XMult2_n_80 : STD_LOGIC;
  signal XMult2_n_81 : STD_LOGIC;
  signal XMult2_n_82 : STD_LOGIC;
  signal XMult2_n_83 : STD_LOGIC;
  signal XMult2_n_84 : STD_LOGIC;
  signal XMult2_n_85 : STD_LOGIC;
  signal XMult2_n_86 : STD_LOGIC;
  signal XMult2_n_87 : STD_LOGIC;
  signal XMult2_n_88 : STD_LOGIC;
  signal XMult2_n_89 : STD_LOGIC;
  signal XMult2_n_9 : STD_LOGIC;
  signal XMult2_n_90 : STD_LOGIC;
  signal XMult2_n_91 : STD_LOGIC;
  signal XMult2_n_92 : STD_LOGIC;
  signal XMult2_n_93 : STD_LOGIC;
  signal XMult2_n_94 : STD_LOGIC;
  signal XMult2_n_95 : STD_LOGIC;
  signal XMult2_n_96 : STD_LOGIC;
  signal XMult2_n_97 : STD_LOGIC;
  signal XMult2_n_98 : STD_LOGIC;
  signal XMult2_n_99 : STD_LOGIC;
  signal \YMult1__0\ : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal YMult1_n_71 : STD_LOGIC;
  signal YMult1_n_72 : STD_LOGIC;
  signal YMult2_n_100 : STD_LOGIC;
  signal YMult2_n_101 : STD_LOGIC;
  signal YMult2_n_102 : STD_LOGIC;
  signal YMult2_n_103 : STD_LOGIC;
  signal YMult2_n_104 : STD_LOGIC;
  signal YMult2_n_105 : STD_LOGIC;
  signal YMult2_n_72 : STD_LOGIC;
  signal YMult2_n_73 : STD_LOGIC;
  signal YMult2_n_74 : STD_LOGIC;
  signal YMult2_n_75 : STD_LOGIC;
  signal YMult2_n_76 : STD_LOGIC;
  signal YMult2_n_77 : STD_LOGIC;
  signal YMult2_n_78 : STD_LOGIC;
  signal YMult2_n_79 : STD_LOGIC;
  signal YMult2_n_80 : STD_LOGIC;
  signal YMult2_n_81 : STD_LOGIC;
  signal YMult2_n_82 : STD_LOGIC;
  signal YMult2_n_83 : STD_LOGIC;
  signal YMult2_n_84 : STD_LOGIC;
  signal YMult2_n_85 : STD_LOGIC;
  signal YMult2_n_86 : STD_LOGIC;
  signal YMult2_n_87 : STD_LOGIC;
  signal YMult2_n_88 : STD_LOGIC;
  signal YMult2_n_89 : STD_LOGIC;
  signal YMult2_n_90 : STD_LOGIC;
  signal YMult2_n_91 : STD_LOGIC;
  signal YMult2_n_92 : STD_LOGIC;
  signal YMult2_n_93 : STD_LOGIC;
  signal YMult2_n_94 : STD_LOGIC;
  signal YMult2_n_95 : STD_LOGIC;
  signal YMult2_n_96 : STD_LOGIC;
  signal YMult2_n_97 : STD_LOGIC;
  signal YMult2_n_98 : STD_LOGIC;
  signal YMult2_n_99 : STD_LOGIC;
  signal Ysum0 : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal \Ysum__0_n_100\ : STD_LOGIC;
  signal \Ysum__0_n_101\ : STD_LOGIC;
  signal \Ysum__0_n_102\ : STD_LOGIC;
  signal \Ysum__0_n_103\ : STD_LOGIC;
  signal \Ysum__0_n_104\ : STD_LOGIC;
  signal \Ysum__0_n_105\ : STD_LOGIC;
  signal \Ysum__0_n_106\ : STD_LOGIC;
  signal \Ysum__0_n_107\ : STD_LOGIC;
  signal \Ysum__0_n_108\ : STD_LOGIC;
  signal \Ysum__0_n_109\ : STD_LOGIC;
  signal \Ysum__0_n_110\ : STD_LOGIC;
  signal \Ysum__0_n_111\ : STD_LOGIC;
  signal \Ysum__0_n_112\ : STD_LOGIC;
  signal \Ysum__0_n_113\ : STD_LOGIC;
  signal \Ysum__0_n_114\ : STD_LOGIC;
  signal \Ysum__0_n_115\ : STD_LOGIC;
  signal \Ysum__0_n_116\ : STD_LOGIC;
  signal \Ysum__0_n_117\ : STD_LOGIC;
  signal \Ysum__0_n_118\ : STD_LOGIC;
  signal \Ysum__0_n_119\ : STD_LOGIC;
  signal \Ysum__0_n_120\ : STD_LOGIC;
  signal \Ysum__0_n_121\ : STD_LOGIC;
  signal \Ysum__0_n_122\ : STD_LOGIC;
  signal \Ysum__0_n_123\ : STD_LOGIC;
  signal \Ysum__0_n_124\ : STD_LOGIC;
  signal \Ysum__0_n_125\ : STD_LOGIC;
  signal \Ysum__0_n_126\ : STD_LOGIC;
  signal \Ysum__0_n_127\ : STD_LOGIC;
  signal \Ysum__0_n_128\ : STD_LOGIC;
  signal \Ysum__0_n_129\ : STD_LOGIC;
  signal \Ysum__0_n_130\ : STD_LOGIC;
  signal \Ysum__0_n_131\ : STD_LOGIC;
  signal \Ysum__0_n_132\ : STD_LOGIC;
  signal \Ysum__0_n_133\ : STD_LOGIC;
  signal \Ysum__0_n_134\ : STD_LOGIC;
  signal \Ysum__0_n_135\ : STD_LOGIC;
  signal \Ysum__0_n_136\ : STD_LOGIC;
  signal \Ysum__0_n_137\ : STD_LOGIC;
  signal \Ysum__0_n_138\ : STD_LOGIC;
  signal \Ysum__0_n_139\ : STD_LOGIC;
  signal \Ysum__0_n_140\ : STD_LOGIC;
  signal \Ysum__0_n_141\ : STD_LOGIC;
  signal \Ysum__0_n_142\ : STD_LOGIC;
  signal \Ysum__0_n_143\ : STD_LOGIC;
  signal \Ysum__0_n_144\ : STD_LOGIC;
  signal \Ysum__0_n_145\ : STD_LOGIC;
  signal \Ysum__0_n_146\ : STD_LOGIC;
  signal \Ysum__0_n_147\ : STD_LOGIC;
  signal \Ysum__0_n_148\ : STD_LOGIC;
  signal \Ysum__0_n_149\ : STD_LOGIC;
  signal \Ysum__0_n_150\ : STD_LOGIC;
  signal \Ysum__0_n_151\ : STD_LOGIC;
  signal \Ysum__0_n_152\ : STD_LOGIC;
  signal \Ysum__0_n_153\ : STD_LOGIC;
  signal \Ysum__0_n_73\ : STD_LOGIC;
  signal \Ysum__0_n_74\ : STD_LOGIC;
  signal \Ysum__0_n_75\ : STD_LOGIC;
  signal \Ysum__0_n_76\ : STD_LOGIC;
  signal \Ysum__0_n_77\ : STD_LOGIC;
  signal \Ysum__0_n_78\ : STD_LOGIC;
  signal \Ysum__0_n_79\ : STD_LOGIC;
  signal \Ysum__0_n_80\ : STD_LOGIC;
  signal \Ysum__0_n_81\ : STD_LOGIC;
  signal \Ysum__0_n_82\ : STD_LOGIC;
  signal \Ysum__0_n_83\ : STD_LOGIC;
  signal \Ysum__0_n_84\ : STD_LOGIC;
  signal \Ysum__0_n_85\ : STD_LOGIC;
  signal \Ysum__0_n_86\ : STD_LOGIC;
  signal \Ysum__0_n_87\ : STD_LOGIC;
  signal \Ysum__0_n_88\ : STD_LOGIC;
  signal \Ysum__0_n_89\ : STD_LOGIC;
  signal \Ysum__0_n_90\ : STD_LOGIC;
  signal \Ysum__0_n_91\ : STD_LOGIC;
  signal \Ysum__0_n_92\ : STD_LOGIC;
  signal \Ysum__0_n_93\ : STD_LOGIC;
  signal \Ysum__0_n_94\ : STD_LOGIC;
  signal \Ysum__0_n_95\ : STD_LOGIC;
  signal \Ysum__0_n_96\ : STD_LOGIC;
  signal \Ysum__0_n_97\ : STD_LOGIC;
  signal \Ysum__0_n_98\ : STD_LOGIC;
  signal \Ysum__0_n_99\ : STD_LOGIC;
  signal \Ysum__1_i_11_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_11_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_11_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_11_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_12_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_12_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_12_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_12_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_13_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_13_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_13_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_13_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_14_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_14_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_14_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_14_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_15_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_15_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_15_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_15_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_16_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_16_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_16_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_16_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_17_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_17_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_17_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_17_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_18_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_18_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_18_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_18_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_19_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_1_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_1_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_1_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_1_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_20_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_21_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_22_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_23_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_24_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_25_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_26_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_27_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_28_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_29_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_2_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_2_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_2_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_2_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_30_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_31_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_32_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_33_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_34_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_35_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_36_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_37_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_38_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_39_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_3_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_3_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_3_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_3_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_40_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_41_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_42_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_43_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_44_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_45_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_46_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_47_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_48_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_49_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_4_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_4_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_4_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_4_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_50_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_51_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_52_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_53_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_54_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_55_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_56_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_57_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_58_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_59_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_5_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_5_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_5_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_5_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_60_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_61_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_62_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_63_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_64_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_65_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_66_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_67_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_68_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_69_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_70_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_71_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_72_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_73_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_74_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_75_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_76_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_77_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_78_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_79_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_7_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_7_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_7_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_7_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_80_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_81_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_82_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_8_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_8_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_8_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_8_n_3\ : STD_LOGIC;
  signal \Ysum__1_i_9_n_0\ : STD_LOGIC;
  signal \Ysum__1_i_9_n_1\ : STD_LOGIC;
  signal \Ysum__1_i_9_n_2\ : STD_LOGIC;
  signal \Ysum__1_i_9_n_3\ : STD_LOGIC;
  signal \Ysum__1_n_100\ : STD_LOGIC;
  signal \Ysum__1_n_101\ : STD_LOGIC;
  signal \Ysum__1_n_102\ : STD_LOGIC;
  signal \Ysum__1_n_103\ : STD_LOGIC;
  signal \Ysum__1_n_104\ : STD_LOGIC;
  signal \Ysum__1_n_105\ : STD_LOGIC;
  signal \Ysum__1_n_89\ : STD_LOGIC;
  signal \Ysum__1_n_90\ : STD_LOGIC;
  signal \Ysum__1_n_91\ : STD_LOGIC;
  signal \Ysum__1_n_92\ : STD_LOGIC;
  signal \Ysum__1_n_93\ : STD_LOGIC;
  signal \Ysum__1_n_94\ : STD_LOGIC;
  signal \Ysum__1_n_95\ : STD_LOGIC;
  signal \Ysum__1_n_96\ : STD_LOGIC;
  signal \Ysum__1_n_97\ : STD_LOGIC;
  signal \Ysum__1_n_98\ : STD_LOGIC;
  signal \Ysum__1_n_99\ : STD_LOGIC;
  signal \Ysum__2\ : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal Ysum_n_100 : STD_LOGIC;
  signal Ysum_n_101 : STD_LOGIC;
  signal Ysum_n_102 : STD_LOGIC;
  signal Ysum_n_103 : STD_LOGIC;
  signal Ysum_n_104 : STD_LOGIC;
  signal Ysum_n_105 : STD_LOGIC;
  signal Ysum_n_106 : STD_LOGIC;
  signal Ysum_n_107 : STD_LOGIC;
  signal Ysum_n_108 : STD_LOGIC;
  signal Ysum_n_109 : STD_LOGIC;
  signal Ysum_n_110 : STD_LOGIC;
  signal Ysum_n_111 : STD_LOGIC;
  signal Ysum_n_112 : STD_LOGIC;
  signal Ysum_n_113 : STD_LOGIC;
  signal Ysum_n_114 : STD_LOGIC;
  signal Ysum_n_115 : STD_LOGIC;
  signal Ysum_n_116 : STD_LOGIC;
  signal Ysum_n_117 : STD_LOGIC;
  signal Ysum_n_118 : STD_LOGIC;
  signal Ysum_n_119 : STD_LOGIC;
  signal Ysum_n_120 : STD_LOGIC;
  signal Ysum_n_121 : STD_LOGIC;
  signal Ysum_n_122 : STD_LOGIC;
  signal Ysum_n_123 : STD_LOGIC;
  signal Ysum_n_124 : STD_LOGIC;
  signal Ysum_n_125 : STD_LOGIC;
  signal Ysum_n_126 : STD_LOGIC;
  signal Ysum_n_127 : STD_LOGIC;
  signal Ysum_n_128 : STD_LOGIC;
  signal Ysum_n_129 : STD_LOGIC;
  signal Ysum_n_130 : STD_LOGIC;
  signal Ysum_n_131 : STD_LOGIC;
  signal Ysum_n_132 : STD_LOGIC;
  signal Ysum_n_133 : STD_LOGIC;
  signal Ysum_n_134 : STD_LOGIC;
  signal Ysum_n_135 : STD_LOGIC;
  signal Ysum_n_136 : STD_LOGIC;
  signal Ysum_n_137 : STD_LOGIC;
  signal Ysum_n_138 : STD_LOGIC;
  signal Ysum_n_139 : STD_LOGIC;
  signal Ysum_n_140 : STD_LOGIC;
  signal Ysum_n_141 : STD_LOGIC;
  signal Ysum_n_142 : STD_LOGIC;
  signal Ysum_n_143 : STD_LOGIC;
  signal Ysum_n_144 : STD_LOGIC;
  signal Ysum_n_145 : STD_LOGIC;
  signal Ysum_n_146 : STD_LOGIC;
  signal Ysum_n_147 : STD_LOGIC;
  signal Ysum_n_148 : STD_LOGIC;
  signal Ysum_n_149 : STD_LOGIC;
  signal Ysum_n_150 : STD_LOGIC;
  signal Ysum_n_151 : STD_LOGIC;
  signal Ysum_n_152 : STD_LOGIC;
  signal Ysum_n_153 : STD_LOGIC;
  signal Ysum_n_73 : STD_LOGIC;
  signal Ysum_n_74 : STD_LOGIC;
  signal Ysum_n_75 : STD_LOGIC;
  signal Ysum_n_76 : STD_LOGIC;
  signal Ysum_n_77 : STD_LOGIC;
  signal Ysum_n_78 : STD_LOGIC;
  signal Ysum_n_79 : STD_LOGIC;
  signal Ysum_n_80 : STD_LOGIC;
  signal Ysum_n_81 : STD_LOGIC;
  signal Ysum_n_82 : STD_LOGIC;
  signal Ysum_n_83 : STD_LOGIC;
  signal Ysum_n_84 : STD_LOGIC;
  signal Ysum_n_85 : STD_LOGIC;
  signal Ysum_n_86 : STD_LOGIC;
  signal Ysum_n_87 : STD_LOGIC;
  signal Ysum_n_88 : STD_LOGIC;
  signal Ysum_n_89 : STD_LOGIC;
  signal Ysum_n_90 : STD_LOGIC;
  signal Ysum_n_91 : STD_LOGIC;
  signal Ysum_n_92 : STD_LOGIC;
  signal Ysum_n_93 : STD_LOGIC;
  signal Ysum_n_94 : STD_LOGIC;
  signal Ysum_n_95 : STD_LOGIC;
  signal Ysum_n_96 : STD_LOGIC;
  signal Ysum_n_97 : STD_LOGIC;
  signal Ysum_n_98 : STD_LOGIC;
  signal Ysum_n_99 : STD_LOGIC;
  signal NLW_XMult2_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_XMult2_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_XMult2_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_XMult2_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_XMult2_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_XMult2_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_XMult2_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_XMult2_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_XMult2_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 28 );
  signal NLW_YMult1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_YMult1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_YMult1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_YMult1_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 35 );
  signal NLW_YMult1_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_YMult2_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_YMult2_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_YMult2_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_YMult2_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 34 );
  signal NLW_YMult2_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_Ysum_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_Ysum_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_Ysum_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_Ysum_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 33 );
  signal \NLW_Ysum__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal \NLW_Ysum__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \NLW_Ysum__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_Ysum__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 33 );
  signal \NLW_Ysum__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal \NLW_Ysum__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \NLW_Ysum__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_Ysum__1_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 33 );
  signal \NLW_Ysum__1_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \NLW_Ysum__1_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_Ysum__1_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_Ysum__1_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_Ysum__1_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of XMult2 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute METHODOLOGY_DRC_VIOS of YMult1 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute METHODOLOGY_DRC_VIOS of YMult2 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute METHODOLOGY_DRC_VIOS of Ysum : label is "{SYNTH-13 {cell *THIS*}}";
  attribute METHODOLOGY_DRC_VIOS of \Ysum__0\ : label is "{SYNTH-13 {cell *THIS*}}";
  attribute METHODOLOGY_DRC_VIOS of \Ysum__1\ : label is "{SYNTH-13 {cell *THIS*}}";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \Ysum__1_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_10\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_11\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_12\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_13\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_14\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_15\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_16\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_17\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_18\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_4\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_5\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_6\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_7\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_8\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__1_i_9\ : label is 35;
begin
XMult2: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29) => Xin2(15),
      A(28) => Xin2(15),
      A(27) => Xin2(15),
      A(26) => Xin2(15),
      A(25) => Xin2(15),
      A(24) => Xin2(15),
      A(23) => Xin2(15),
      A(22) => Xin2(15),
      A(21) => Xin2(15),
      A(20) => Xin2(15),
      A(19) => Xin2(15),
      A(18) => Xin2(15),
      A(17) => Xin2(15),
      A(16) => Xin2(15),
      A(15 downto 0) => Xin2(15 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_XMult2_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 0) => B"000000011001100100",
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17) => XMult2_n_6,
      BCOUT(16) => XMult2_n_7,
      BCOUT(15) => XMult2_n_8,
      BCOUT(14) => XMult2_n_9,
      BCOUT(13) => XMult2_n_10,
      BCOUT(12) => XMult2_n_11,
      BCOUT(11) => XMult2_n_12,
      BCOUT(10) => XMult2_n_13,
      BCOUT(9) => XMult2_n_14,
      BCOUT(8) => XMult2_n_15,
      BCOUT(7) => XMult2_n_16,
      BCOUT(6) => XMult2_n_17,
      BCOUT(5) => XMult2_n_18,
      BCOUT(4) => XMult2_n_19,
      BCOUT(3) => XMult2_n_20,
      BCOUT(2) => XMult2_n_21,
      BCOUT(1) => XMult2_n_22,
      BCOUT(0) => XMult2_n_23,
      C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_XMult2_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_XMult2_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_XMult2_MULTSIGNOUT_UNCONNECTED,
      OPMODE(6 downto 0) => B"0000101",
      OVERFLOW => NLW_XMult2_OVERFLOW_UNCONNECTED,
      P(47 downto 28) => NLW_XMult2_P_UNCONNECTED(47 downto 28),
      P(27) => XMult2_n_78,
      P(26) => XMult2_n_79,
      P(25) => XMult2_n_80,
      P(24) => XMult2_n_81,
      P(23) => XMult2_n_82,
      P(22) => XMult2_n_83,
      P(21) => XMult2_n_84,
      P(20) => XMult2_n_85,
      P(19) => XMult2_n_86,
      P(18) => XMult2_n_87,
      P(17) => XMult2_n_88,
      P(16) => XMult2_n_89,
      P(15) => XMult2_n_90,
      P(14) => XMult2_n_91,
      P(13) => XMult2_n_92,
      P(12) => XMult2_n_93,
      P(11) => XMult2_n_94,
      P(10) => XMult2_n_95,
      P(9) => XMult2_n_96,
      P(8) => XMult2_n_97,
      P(7) => XMult2_n_98,
      P(6) => XMult2_n_99,
      P(5) => XMult2_n_100,
      P(4) => XMult2_n_101,
      P(3) => XMult2_n_102,
      P(2) => XMult2_n_103,
      P(1) => XMult2_n_104,
      P(0) => XMult2_n_105,
      PATTERNBDETECT => NLW_XMult2_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_XMult2_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47) => XMult2_n_106,
      PCOUT(46) => XMult2_n_107,
      PCOUT(45) => XMult2_n_108,
      PCOUT(44) => XMult2_n_109,
      PCOUT(43) => XMult2_n_110,
      PCOUT(42) => XMult2_n_111,
      PCOUT(41) => XMult2_n_112,
      PCOUT(40) => XMult2_n_113,
      PCOUT(39) => XMult2_n_114,
      PCOUT(38) => XMult2_n_115,
      PCOUT(37) => XMult2_n_116,
      PCOUT(36) => XMult2_n_117,
      PCOUT(35) => XMult2_n_118,
      PCOUT(34) => XMult2_n_119,
      PCOUT(33) => XMult2_n_120,
      PCOUT(32) => XMult2_n_121,
      PCOUT(31) => XMult2_n_122,
      PCOUT(30) => XMult2_n_123,
      PCOUT(29) => XMult2_n_124,
      PCOUT(28) => XMult2_n_125,
      PCOUT(27) => XMult2_n_126,
      PCOUT(26) => XMult2_n_127,
      PCOUT(25) => XMult2_n_128,
      PCOUT(24) => XMult2_n_129,
      PCOUT(23) => XMult2_n_130,
      PCOUT(22) => XMult2_n_131,
      PCOUT(21) => XMult2_n_132,
      PCOUT(20) => XMult2_n_133,
      PCOUT(19) => XMult2_n_134,
      PCOUT(18) => XMult2_n_135,
      PCOUT(17) => XMult2_n_136,
      PCOUT(16) => XMult2_n_137,
      PCOUT(15) => XMult2_n_138,
      PCOUT(14) => XMult2_n_139,
      PCOUT(13) => XMult2_n_140,
      PCOUT(12) => XMult2_n_141,
      PCOUT(11) => XMult2_n_142,
      PCOUT(10) => XMult2_n_143,
      PCOUT(9) => XMult2_n_144,
      PCOUT(8) => XMult2_n_145,
      PCOUT(7) => XMult2_n_146,
      PCOUT(6) => XMult2_n_147,
      PCOUT(5) => XMult2_n_148,
      PCOUT(4) => XMult2_n_149,
      PCOUT(3) => XMult2_n_150,
      PCOUT(2) => XMult2_n_151,
      PCOUT(1) => XMult2_n_152,
      PCOUT(0) => XMult2_n_153,
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_XMult2_UNDERFLOW_UNCONNECTED
    );
YMult1: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29 downto 0) => B"111111111111010010100001011101",
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_YMult1_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => Yin1(15),
      B(16) => Yin1(15),
      B(15 downto 0) => Yin1(15 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_YMult1_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_YMult1_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_YMult1_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_YMult1_MULTSIGNOUT_UNCONNECTED,
      OPMODE(6 downto 0) => B"0000101",
      OVERFLOW => NLW_YMult1_OVERFLOW_UNCONNECTED,
      P(47 downto 35) => NLW_YMult1_P_UNCONNECTED(47 downto 35),
      P(34) => YMult1_n_71,
      P(33) => YMult1_n_72,
      P(32 downto 0) => \YMult1__0\(32 downto 0),
      PATTERNBDETECT => NLW_YMult1_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_YMult1_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47 downto 0) => NLW_YMult1_PCOUT_UNCONNECTED(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_YMult1_UNDERFLOW_UNCONNECTED
    );
YMult2: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29) => Yin2(15),
      A(28) => Yin2(15),
      A(27) => Yin2(15),
      A(26) => Yin2(15),
      A(25) => Yin2(15),
      A(24) => Yin2(15),
      A(23) => Yin2(15),
      A(22) => Yin2(15),
      A(21) => Yin2(15),
      A(20) => Yin2(15),
      A(19) => Yin2(15),
      A(18) => Yin2(15),
      A(17) => Yin2(15),
      A(16) => Yin2(15),
      A(15 downto 0) => Yin2(15 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_YMult2_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 0) => B"010000100101001011",
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_YMult2_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_YMult2_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_YMult2_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_YMult2_MULTSIGNOUT_UNCONNECTED,
      OPMODE(6 downto 0) => B"0000101",
      OVERFLOW => NLW_YMult2_OVERFLOW_UNCONNECTED,
      P(47 downto 34) => NLW_YMult2_P_UNCONNECTED(47 downto 34),
      P(33) => YMult2_n_72,
      P(32) => YMult2_n_73,
      P(31) => YMult2_n_74,
      P(30) => YMult2_n_75,
      P(29) => YMult2_n_76,
      P(28) => YMult2_n_77,
      P(27) => YMult2_n_78,
      P(26) => YMult2_n_79,
      P(25) => YMult2_n_80,
      P(24) => YMult2_n_81,
      P(23) => YMult2_n_82,
      P(22) => YMult2_n_83,
      P(21) => YMult2_n_84,
      P(20) => YMult2_n_85,
      P(19) => YMult2_n_86,
      P(18) => YMult2_n_87,
      P(17) => YMult2_n_88,
      P(16) => YMult2_n_89,
      P(15) => YMult2_n_90,
      P(14) => YMult2_n_91,
      P(13) => YMult2_n_92,
      P(12) => YMult2_n_93,
      P(11) => YMult2_n_94,
      P(10) => YMult2_n_95,
      P(9) => YMult2_n_96,
      P(8) => YMult2_n_97,
      P(7) => YMult2_n_98,
      P(6) => YMult2_n_99,
      P(5) => YMult2_n_100,
      P(4) => YMult2_n_101,
      P(3) => YMult2_n_102,
      P(2) => YMult2_n_103,
      P(1) => YMult2_n_104,
      P(0) => YMult2_n_105,
      PATTERNBDETECT => NLW_YMult2_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_YMult2_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47 downto 0) => NLW_YMult2_PCOUT_UNCONNECTED(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_YMult2_UNDERFLOW_UNCONNECTED
    );
Ysum: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "CASCADE",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29) => Xin(15),
      A(28) => Xin(15),
      A(27) => Xin(15),
      A(26) => Xin(15),
      A(25) => Xin(15),
      A(24) => Xin(15),
      A(23) => Xin(15),
      A(22) => Xin(15),
      A(21) => Xin(15),
      A(20) => Xin(15),
      A(19) => Xin(15),
      A(18) => Xin(15),
      A(17) => Xin(15),
      A(16) => Xin(15),
      A(15 downto 0) => Xin(15 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_Ysum_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 0) => B"000000000000000000",
      BCIN(17) => XMult2_n_6,
      BCIN(16) => XMult2_n_7,
      BCIN(15) => XMult2_n_8,
      BCIN(14) => XMult2_n_9,
      BCIN(13) => XMult2_n_10,
      BCIN(12) => XMult2_n_11,
      BCIN(11) => XMult2_n_12,
      BCIN(10) => XMult2_n_13,
      BCIN(9) => XMult2_n_14,
      BCIN(8) => XMult2_n_15,
      BCIN(7) => XMult2_n_16,
      BCIN(6) => XMult2_n_17,
      BCIN(5) => XMult2_n_18,
      BCIN(4) => XMult2_n_19,
      BCIN(3) => XMult2_n_20,
      BCIN(2) => XMult2_n_21,
      BCIN(1) => XMult2_n_22,
      BCIN(0) => XMult2_n_23,
      BCOUT(17 downto 0) => NLW_Ysum_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_Ysum_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_Ysum_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_Ysum_MULTSIGNOUT_UNCONNECTED,
      OPMODE(6 downto 0) => B"0010101",
      OVERFLOW => NLW_Ysum_OVERFLOW_UNCONNECTED,
      P(47 downto 33) => NLW_Ysum_P_UNCONNECTED(47 downto 33),
      P(32) => Ysum_n_73,
      P(31) => Ysum_n_74,
      P(30) => Ysum_n_75,
      P(29) => Ysum_n_76,
      P(28) => Ysum_n_77,
      P(27) => Ysum_n_78,
      P(26) => Ysum_n_79,
      P(25) => Ysum_n_80,
      P(24) => Ysum_n_81,
      P(23) => Ysum_n_82,
      P(22) => Ysum_n_83,
      P(21) => Ysum_n_84,
      P(20) => Ysum_n_85,
      P(19) => Ysum_n_86,
      P(18) => Ysum_n_87,
      P(17) => Ysum_n_88,
      P(16) => Ysum_n_89,
      P(15) => Ysum_n_90,
      P(14) => Ysum_n_91,
      P(13) => Ysum_n_92,
      P(12) => Ysum_n_93,
      P(11) => Ysum_n_94,
      P(10) => Ysum_n_95,
      P(9) => Ysum_n_96,
      P(8) => Ysum_n_97,
      P(7) => Ysum_n_98,
      P(6) => Ysum_n_99,
      P(5) => Ysum_n_100,
      P(4) => Ysum_n_101,
      P(3) => Ysum_n_102,
      P(2) => Ysum_n_103,
      P(1) => Ysum_n_104,
      P(0) => Ysum_n_105,
      PATTERNBDETECT => NLW_Ysum_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_Ysum_PATTERNDETECT_UNCONNECTED,
      PCIN(47) => XMult2_n_106,
      PCIN(46) => XMult2_n_107,
      PCIN(45) => XMult2_n_108,
      PCIN(44) => XMult2_n_109,
      PCIN(43) => XMult2_n_110,
      PCIN(42) => XMult2_n_111,
      PCIN(41) => XMult2_n_112,
      PCIN(40) => XMult2_n_113,
      PCIN(39) => XMult2_n_114,
      PCIN(38) => XMult2_n_115,
      PCIN(37) => XMult2_n_116,
      PCIN(36) => XMult2_n_117,
      PCIN(35) => XMult2_n_118,
      PCIN(34) => XMult2_n_119,
      PCIN(33) => XMult2_n_120,
      PCIN(32) => XMult2_n_121,
      PCIN(31) => XMult2_n_122,
      PCIN(30) => XMult2_n_123,
      PCIN(29) => XMult2_n_124,
      PCIN(28) => XMult2_n_125,
      PCIN(27) => XMult2_n_126,
      PCIN(26) => XMult2_n_127,
      PCIN(25) => XMult2_n_128,
      PCIN(24) => XMult2_n_129,
      PCIN(23) => XMult2_n_130,
      PCIN(22) => XMult2_n_131,
      PCIN(21) => XMult2_n_132,
      PCIN(20) => XMult2_n_133,
      PCIN(19) => XMult2_n_134,
      PCIN(18) => XMult2_n_135,
      PCIN(17) => XMult2_n_136,
      PCIN(16) => XMult2_n_137,
      PCIN(15) => XMult2_n_138,
      PCIN(14) => XMult2_n_139,
      PCIN(13) => XMult2_n_140,
      PCIN(12) => XMult2_n_141,
      PCIN(11) => XMult2_n_142,
      PCIN(10) => XMult2_n_143,
      PCIN(9) => XMult2_n_144,
      PCIN(8) => XMult2_n_145,
      PCIN(7) => XMult2_n_146,
      PCIN(6) => XMult2_n_147,
      PCIN(5) => XMult2_n_148,
      PCIN(4) => XMult2_n_149,
      PCIN(3) => XMult2_n_150,
      PCIN(2) => XMult2_n_151,
      PCIN(1) => XMult2_n_152,
      PCIN(0) => XMult2_n_153,
      PCOUT(47) => Ysum_n_106,
      PCOUT(46) => Ysum_n_107,
      PCOUT(45) => Ysum_n_108,
      PCOUT(44) => Ysum_n_109,
      PCOUT(43) => Ysum_n_110,
      PCOUT(42) => Ysum_n_111,
      PCOUT(41) => Ysum_n_112,
      PCOUT(40) => Ysum_n_113,
      PCOUT(39) => Ysum_n_114,
      PCOUT(38) => Ysum_n_115,
      PCOUT(37) => Ysum_n_116,
      PCOUT(36) => Ysum_n_117,
      PCOUT(35) => Ysum_n_118,
      PCOUT(34) => Ysum_n_119,
      PCOUT(33) => Ysum_n_120,
      PCOUT(32) => Ysum_n_121,
      PCOUT(31) => Ysum_n_122,
      PCOUT(30) => Ysum_n_123,
      PCOUT(29) => Ysum_n_124,
      PCOUT(28) => Ysum_n_125,
      PCOUT(27) => Ysum_n_126,
      PCOUT(26) => Ysum_n_127,
      PCOUT(25) => Ysum_n_128,
      PCOUT(24) => Ysum_n_129,
      PCOUT(23) => Ysum_n_130,
      PCOUT(22) => Ysum_n_131,
      PCOUT(21) => Ysum_n_132,
      PCOUT(20) => Ysum_n_133,
      PCOUT(19) => Ysum_n_134,
      PCOUT(18) => Ysum_n_135,
      PCOUT(17) => Ysum_n_136,
      PCOUT(16) => Ysum_n_137,
      PCOUT(15) => Ysum_n_138,
      PCOUT(14) => Ysum_n_139,
      PCOUT(13) => Ysum_n_140,
      PCOUT(12) => Ysum_n_141,
      PCOUT(11) => Ysum_n_142,
      PCOUT(10) => Ysum_n_143,
      PCOUT(9) => Ysum_n_144,
      PCOUT(8) => Ysum_n_145,
      PCOUT(7) => Ysum_n_146,
      PCOUT(6) => Ysum_n_147,
      PCOUT(5) => Ysum_n_148,
      PCOUT(4) => Ysum_n_149,
      PCOUT(3) => Ysum_n_150,
      PCOUT(2) => Ysum_n_151,
      PCOUT(1) => Ysum_n_152,
      PCOUT(0) => Ysum_n_153,
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_Ysum_UNDERFLOW_UNCONNECTED
    );
\Ysum__0\: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29) => Xin1(15),
      A(28) => Xin1(15),
      A(27) => Xin1(15),
      A(26) => Xin1(15),
      A(25) => Xin1(15),
      A(24) => Xin1(15),
      A(23) => Xin1(15),
      A(22) => Xin1(15),
      A(21) => Xin1(15),
      A(20) => Xin1(15),
      A(19) => Xin1(15),
      A(18) => Xin1(15),
      A(17) => Xin1(15),
      A(16) => Xin1(15),
      A(15 downto 0) => Xin1(15 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => \NLW_Ysum__0_ACOUT_UNCONNECTED\(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 0) => B"111111110111101101",
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => \NLW_Ysum__0_BCOUT_UNCONNECTED\(17 downto 0),
      C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
      CARRYCASCIN => '0',
      CARRYCASCOUT => \NLW_Ysum__0_CARRYCASCOUT_UNCONNECTED\,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => \NLW_Ysum__0_CARRYOUT_UNCONNECTED\(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => \NLW_Ysum__0_MULTSIGNOUT_UNCONNECTED\,
      OPMODE(6 downto 0) => B"0010101",
      OVERFLOW => \NLW_Ysum__0_OVERFLOW_UNCONNECTED\,
      P(47 downto 33) => \NLW_Ysum__0_P_UNCONNECTED\(47 downto 33),
      P(32) => \Ysum__0_n_73\,
      P(31) => \Ysum__0_n_74\,
      P(30) => \Ysum__0_n_75\,
      P(29) => \Ysum__0_n_76\,
      P(28) => \Ysum__0_n_77\,
      P(27) => \Ysum__0_n_78\,
      P(26) => \Ysum__0_n_79\,
      P(25) => \Ysum__0_n_80\,
      P(24) => \Ysum__0_n_81\,
      P(23) => \Ysum__0_n_82\,
      P(22) => \Ysum__0_n_83\,
      P(21) => \Ysum__0_n_84\,
      P(20) => \Ysum__0_n_85\,
      P(19) => \Ysum__0_n_86\,
      P(18) => \Ysum__0_n_87\,
      P(17) => \Ysum__0_n_88\,
      P(16) => \Ysum__0_n_89\,
      P(15) => \Ysum__0_n_90\,
      P(14) => \Ysum__0_n_91\,
      P(13) => \Ysum__0_n_92\,
      P(12) => \Ysum__0_n_93\,
      P(11) => \Ysum__0_n_94\,
      P(10) => \Ysum__0_n_95\,
      P(9) => \Ysum__0_n_96\,
      P(8) => \Ysum__0_n_97\,
      P(7) => \Ysum__0_n_98\,
      P(6) => \Ysum__0_n_99\,
      P(5) => \Ysum__0_n_100\,
      P(4) => \Ysum__0_n_101\,
      P(3) => \Ysum__0_n_102\,
      P(2) => \Ysum__0_n_103\,
      P(1) => \Ysum__0_n_104\,
      P(0) => \Ysum__0_n_105\,
      PATTERNBDETECT => \NLW_Ysum__0_PATTERNBDETECT_UNCONNECTED\,
      PATTERNDETECT => \NLW_Ysum__0_PATTERNDETECT_UNCONNECTED\,
      PCIN(47) => Ysum_n_106,
      PCIN(46) => Ysum_n_107,
      PCIN(45) => Ysum_n_108,
      PCIN(44) => Ysum_n_109,
      PCIN(43) => Ysum_n_110,
      PCIN(42) => Ysum_n_111,
      PCIN(41) => Ysum_n_112,
      PCIN(40) => Ysum_n_113,
      PCIN(39) => Ysum_n_114,
      PCIN(38) => Ysum_n_115,
      PCIN(37) => Ysum_n_116,
      PCIN(36) => Ysum_n_117,
      PCIN(35) => Ysum_n_118,
      PCIN(34) => Ysum_n_119,
      PCIN(33) => Ysum_n_120,
      PCIN(32) => Ysum_n_121,
      PCIN(31) => Ysum_n_122,
      PCIN(30) => Ysum_n_123,
      PCIN(29) => Ysum_n_124,
      PCIN(28) => Ysum_n_125,
      PCIN(27) => Ysum_n_126,
      PCIN(26) => Ysum_n_127,
      PCIN(25) => Ysum_n_128,
      PCIN(24) => Ysum_n_129,
      PCIN(23) => Ysum_n_130,
      PCIN(22) => Ysum_n_131,
      PCIN(21) => Ysum_n_132,
      PCIN(20) => Ysum_n_133,
      PCIN(19) => Ysum_n_134,
      PCIN(18) => Ysum_n_135,
      PCIN(17) => Ysum_n_136,
      PCIN(16) => Ysum_n_137,
      PCIN(15) => Ysum_n_138,
      PCIN(14) => Ysum_n_139,
      PCIN(13) => Ysum_n_140,
      PCIN(12) => Ysum_n_141,
      PCIN(11) => Ysum_n_142,
      PCIN(10) => Ysum_n_143,
      PCIN(9) => Ysum_n_144,
      PCIN(8) => Ysum_n_145,
      PCIN(7) => Ysum_n_146,
      PCIN(6) => Ysum_n_147,
      PCIN(5) => Ysum_n_148,
      PCIN(4) => Ysum_n_149,
      PCIN(3) => Ysum_n_150,
      PCIN(2) => Ysum_n_151,
      PCIN(1) => Ysum_n_152,
      PCIN(0) => Ysum_n_153,
      PCOUT(47) => \Ysum__0_n_106\,
      PCOUT(46) => \Ysum__0_n_107\,
      PCOUT(45) => \Ysum__0_n_108\,
      PCOUT(44) => \Ysum__0_n_109\,
      PCOUT(43) => \Ysum__0_n_110\,
      PCOUT(42) => \Ysum__0_n_111\,
      PCOUT(41) => \Ysum__0_n_112\,
      PCOUT(40) => \Ysum__0_n_113\,
      PCOUT(39) => \Ysum__0_n_114\,
      PCOUT(38) => \Ysum__0_n_115\,
      PCOUT(37) => \Ysum__0_n_116\,
      PCOUT(36) => \Ysum__0_n_117\,
      PCOUT(35) => \Ysum__0_n_118\,
      PCOUT(34) => \Ysum__0_n_119\,
      PCOUT(33) => \Ysum__0_n_120\,
      PCOUT(32) => \Ysum__0_n_121\,
      PCOUT(31) => \Ysum__0_n_122\,
      PCOUT(30) => \Ysum__0_n_123\,
      PCOUT(29) => \Ysum__0_n_124\,
      PCOUT(28) => \Ysum__0_n_125\,
      PCOUT(27) => \Ysum__0_n_126\,
      PCOUT(26) => \Ysum__0_n_127\,
      PCOUT(25) => \Ysum__0_n_128\,
      PCOUT(24) => \Ysum__0_n_129\,
      PCOUT(23) => \Ysum__0_n_130\,
      PCOUT(22) => \Ysum__0_n_131\,
      PCOUT(21) => \Ysum__0_n_132\,
      PCOUT(20) => \Ysum__0_n_133\,
      PCOUT(19) => \Ysum__0_n_134\,
      PCOUT(18) => \Ysum__0_n_135\,
      PCOUT(17) => \Ysum__0_n_136\,
      PCOUT(16) => \Ysum__0_n_137\,
      PCOUT(15) => \Ysum__0_n_138\,
      PCOUT(14) => \Ysum__0_n_139\,
      PCOUT(13) => \Ysum__0_n_140\,
      PCOUT(12) => \Ysum__0_n_141\,
      PCOUT(11) => \Ysum__0_n_142\,
      PCOUT(10) => \Ysum__0_n_143\,
      PCOUT(9) => \Ysum__0_n_144\,
      PCOUT(8) => \Ysum__0_n_145\,
      PCOUT(7) => \Ysum__0_n_146\,
      PCOUT(6) => \Ysum__0_n_147\,
      PCOUT(5) => \Ysum__0_n_148\,
      PCOUT(4) => \Ysum__0_n_149\,
      PCOUT(3) => \Ysum__0_n_150\,
      PCOUT(2) => \Ysum__0_n_151\,
      PCOUT(1) => \Ysum__0_n_152\,
      PCOUT(0) => \Ysum__0_n_153\,
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => \NLW_Ysum__0_UNDERFLOW_UNCONNECTED\
    );
\Ysum__1\: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 0,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "NONE",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29) => Ysum0(32),
      A(28) => Ysum0(32),
      A(27) => Ysum0(32),
      A(26) => Ysum0(32),
      A(25) => Ysum0(32),
      A(24) => Ysum0(32),
      A(23) => Ysum0(32),
      A(22) => Ysum0(32),
      A(21) => Ysum0(32),
      A(20) => Ysum0(32),
      A(19) => Ysum0(32),
      A(18) => Ysum0(32),
      A(17) => Ysum0(32),
      A(16) => Ysum0(32),
      A(15) => Ysum0(32),
      A(14 downto 0) => Ysum0(32 downto 18),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => \NLW_Ysum__1_ACOUT_UNCONNECTED\(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 0) => Ysum0(17 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => \NLW_Ysum__1_BCOUT_UNCONNECTED\(17 downto 0),
      C(47) => \Ysum__2\(32),
      C(46) => \Ysum__2\(32),
      C(45) => \Ysum__2\(32),
      C(44) => \Ysum__2\(32),
      C(43) => \Ysum__2\(32),
      C(42) => \Ysum__2\(32),
      C(41) => \Ysum__2\(32),
      C(40) => \Ysum__2\(32),
      C(39) => \Ysum__2\(32),
      C(38) => \Ysum__2\(32),
      C(37) => \Ysum__2\(32),
      C(36) => \Ysum__2\(32),
      C(35) => \Ysum__2\(32),
      C(34) => \Ysum__2\(32),
      C(33) => \Ysum__2\(32),
      C(32 downto 0) => \Ysum__2\(32 downto 0),
      CARRYCASCIN => '0',
      CARRYCASCOUT => \NLW_Ysum__1_CARRYCASCOUT_UNCONNECTED\,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => \NLW_Ysum__1_CARRYOUT_UNCONNECTED\(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => \NLW_Ysum__1_MULTSIGNOUT_UNCONNECTED\,
      OPMODE(6 downto 0) => B"0011111",
      OVERFLOW => \NLW_Ysum__1_OVERFLOW_UNCONNECTED\,
      P(47 downto 33) => \NLW_Ysum__1_P_UNCONNECTED\(47 downto 33),
      P(32 downto 17) => Yout(15 downto 0),
      P(16) => \Ysum__1_n_89\,
      P(15) => \Ysum__1_n_90\,
      P(14) => \Ysum__1_n_91\,
      P(13) => \Ysum__1_n_92\,
      P(12) => \Ysum__1_n_93\,
      P(11) => \Ysum__1_n_94\,
      P(10) => \Ysum__1_n_95\,
      P(9) => \Ysum__1_n_96\,
      P(8) => \Ysum__1_n_97\,
      P(7) => \Ysum__1_n_98\,
      P(6) => \Ysum__1_n_99\,
      P(5) => \Ysum__1_n_100\,
      P(4) => \Ysum__1_n_101\,
      P(3) => \Ysum__1_n_102\,
      P(2) => \Ysum__1_n_103\,
      P(1) => \Ysum__1_n_104\,
      P(0) => \Ysum__1_n_105\,
      PATTERNBDETECT => \NLW_Ysum__1_PATTERNBDETECT_UNCONNECTED\,
      PATTERNDETECT => \NLW_Ysum__1_PATTERNDETECT_UNCONNECTED\,
      PCIN(47) => \Ysum__0_n_106\,
      PCIN(46) => \Ysum__0_n_107\,
      PCIN(45) => \Ysum__0_n_108\,
      PCIN(44) => \Ysum__0_n_109\,
      PCIN(43) => \Ysum__0_n_110\,
      PCIN(42) => \Ysum__0_n_111\,
      PCIN(41) => \Ysum__0_n_112\,
      PCIN(40) => \Ysum__0_n_113\,
      PCIN(39) => \Ysum__0_n_114\,
      PCIN(38) => \Ysum__0_n_115\,
      PCIN(37) => \Ysum__0_n_116\,
      PCIN(36) => \Ysum__0_n_117\,
      PCIN(35) => \Ysum__0_n_118\,
      PCIN(34) => \Ysum__0_n_119\,
      PCIN(33) => \Ysum__0_n_120\,
      PCIN(32) => \Ysum__0_n_121\,
      PCIN(31) => \Ysum__0_n_122\,
      PCIN(30) => \Ysum__0_n_123\,
      PCIN(29) => \Ysum__0_n_124\,
      PCIN(28) => \Ysum__0_n_125\,
      PCIN(27) => \Ysum__0_n_126\,
      PCIN(26) => \Ysum__0_n_127\,
      PCIN(25) => \Ysum__0_n_128\,
      PCIN(24) => \Ysum__0_n_129\,
      PCIN(23) => \Ysum__0_n_130\,
      PCIN(22) => \Ysum__0_n_131\,
      PCIN(21) => \Ysum__0_n_132\,
      PCIN(20) => \Ysum__0_n_133\,
      PCIN(19) => \Ysum__0_n_134\,
      PCIN(18) => \Ysum__0_n_135\,
      PCIN(17) => \Ysum__0_n_136\,
      PCIN(16) => \Ysum__0_n_137\,
      PCIN(15) => \Ysum__0_n_138\,
      PCIN(14) => \Ysum__0_n_139\,
      PCIN(13) => \Ysum__0_n_140\,
      PCIN(12) => \Ysum__0_n_141\,
      PCIN(11) => \Ysum__0_n_142\,
      PCIN(10) => \Ysum__0_n_143\,
      PCIN(9) => \Ysum__0_n_144\,
      PCIN(8) => \Ysum__0_n_145\,
      PCIN(7) => \Ysum__0_n_146\,
      PCIN(6) => \Ysum__0_n_147\,
      PCIN(5) => \Ysum__0_n_148\,
      PCIN(4) => \Ysum__0_n_149\,
      PCIN(3) => \Ysum__0_n_150\,
      PCIN(2) => \Ysum__0_n_151\,
      PCIN(1) => \Ysum__0_n_152\,
      PCIN(0) => \Ysum__0_n_153\,
      PCOUT(47 downto 0) => \NLW_Ysum__1_PCOUT_UNCONNECTED\(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => \NLW_Ysum__1_UNDERFLOW_UNCONNECTED\
    );
\Ysum__1_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_2_n_0\,
      CO(3) => \Ysum__1_i_1_n_0\,
      CO(2) => \Ysum__1_i_1_n_1\,
      CO(1) => \Ysum__1_i_1_n_2\,
      CO(0) => \Ysum__1_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(19 downto 16),
      S(3) => \Ysum__1_i_19_n_0\,
      S(2) => \Ysum__1_i_20_n_0\,
      S(1) => \Ysum__1_i_21_n_0\,
      S(0) => \Ysum__1_i_22_n_0\
    );
\Ysum__1_i_10\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_11_n_0\,
      CO(3 downto 0) => \NLW_Ysum__1_i_10_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_Ysum__1_i_10_O_UNCONNECTED\(3 downto 1),
      O(0) => \Ysum__2\(32),
      S(3 downto 1) => B"000",
      S(0) => \Ysum__1_i_51_n_0\
    );
\Ysum__1_i_11\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_12_n_0\,
      CO(3) => \Ysum__1_i_11_n_0\,
      CO(2) => \Ysum__1_i_11_n_1\,
      CO(1) => \Ysum__1_i_11_n_2\,
      CO(0) => \Ysum__1_i_11_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__2\(31 downto 28),
      S(3) => \Ysum__1_i_52_n_0\,
      S(2) => \Ysum__1_i_53_n_0\,
      S(1) => \Ysum__1_i_54_n_0\,
      S(0) => \Ysum__1_i_55_n_0\
    );
\Ysum__1_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_13_n_0\,
      CO(3) => \Ysum__1_i_12_n_0\,
      CO(2) => \Ysum__1_i_12_n_1\,
      CO(1) => \Ysum__1_i_12_n_2\,
      CO(0) => \Ysum__1_i_12_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__2\(27 downto 24),
      S(3) => \Ysum__1_i_56_n_0\,
      S(2) => \Ysum__1_i_57_n_0\,
      S(1) => \Ysum__1_i_58_n_0\,
      S(0) => \Ysum__1_i_59_n_0\
    );
\Ysum__1_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_14_n_0\,
      CO(3) => \Ysum__1_i_13_n_0\,
      CO(2) => \Ysum__1_i_13_n_1\,
      CO(1) => \Ysum__1_i_13_n_2\,
      CO(0) => \Ysum__1_i_13_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__2\(23 downto 20),
      S(3) => \Ysum__1_i_60_n_0\,
      S(2) => \Ysum__1_i_61_n_0\,
      S(1) => \Ysum__1_i_62_n_0\,
      S(0) => \Ysum__1_i_63_n_0\
    );
\Ysum__1_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_15_n_0\,
      CO(3) => \Ysum__1_i_14_n_0\,
      CO(2) => \Ysum__1_i_14_n_1\,
      CO(1) => \Ysum__1_i_14_n_2\,
      CO(0) => \Ysum__1_i_14_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__2\(19 downto 16),
      S(3) => \Ysum__1_i_64_n_0\,
      S(2) => \Ysum__1_i_65_n_0\,
      S(1) => \Ysum__1_i_66_n_0\,
      S(0) => \Ysum__1_i_67_n_0\
    );
\Ysum__1_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_16_n_0\,
      CO(3) => \Ysum__1_i_15_n_0\,
      CO(2) => \Ysum__1_i_15_n_1\,
      CO(1) => \Ysum__1_i_15_n_2\,
      CO(0) => \Ysum__1_i_15_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__2\(15 downto 12),
      S(3) => \Ysum__1_i_68_n_0\,
      S(2) => \Ysum__1_i_69_n_0\,
      S(1) => \Ysum__1_i_70_n_0\,
      S(0) => \Ysum__1_i_71_n_0\
    );
\Ysum__1_i_16\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_17_n_0\,
      CO(3) => \Ysum__1_i_16_n_0\,
      CO(2) => \Ysum__1_i_16_n_1\,
      CO(1) => \Ysum__1_i_16_n_2\,
      CO(0) => \Ysum__1_i_16_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__2\(11 downto 8),
      S(3) => \Ysum__1_i_72_n_0\,
      S(2) => \Ysum__1_i_73_n_0\,
      S(1) => \Ysum__1_i_74_n_0\,
      S(0) => \Ysum__1_i_75_n_0\
    );
\Ysum__1_i_17\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_18_n_0\,
      CO(3) => \Ysum__1_i_17_n_0\,
      CO(2) => \Ysum__1_i_17_n_1\,
      CO(1) => \Ysum__1_i_17_n_2\,
      CO(0) => \Ysum__1_i_17_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__2\(7 downto 4),
      S(3) => \Ysum__1_i_76_n_0\,
      S(2) => \Ysum__1_i_77_n_0\,
      S(1) => \Ysum__1_i_78_n_0\,
      S(0) => \Ysum__1_i_79_n_0\
    );
\Ysum__1_i_18\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \Ysum__1_i_18_n_0\,
      CO(2) => \Ysum__1_i_18_n_1\,
      CO(1) => \Ysum__1_i_18_n_2\,
      CO(0) => \Ysum__1_i_18_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3 downto 0) => \Ysum__2\(3 downto 0),
      S(3) => \Ysum__1_i_80_n_0\,
      S(2) => \Ysum__1_i_81_n_0\,
      S(1) => \Ysum__1_i_82_n_0\,
      S(0) => YMult2_n_105
    );
\Ysum__1_i_19\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(19),
      O => \Ysum__1_i_19_n_0\
    );
\Ysum__1_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_3_n_0\,
      CO(3) => \Ysum__1_i_2_n_0\,
      CO(2) => \Ysum__1_i_2_n_1\,
      CO(1) => \Ysum__1_i_2_n_2\,
      CO(0) => \Ysum__1_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(15 downto 12),
      S(3) => \Ysum__1_i_23_n_0\,
      S(2) => \Ysum__1_i_24_n_0\,
      S(1) => \Ysum__1_i_25_n_0\,
      S(0) => \Ysum__1_i_26_n_0\
    );
\Ysum__1_i_20\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(18),
      O => \Ysum__1_i_20_n_0\
    );
\Ysum__1_i_21\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(17),
      O => \Ysum__1_i_21_n_0\
    );
\Ysum__1_i_22\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(16),
      O => \Ysum__1_i_22_n_0\
    );
\Ysum__1_i_23\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(15),
      O => \Ysum__1_i_23_n_0\
    );
\Ysum__1_i_24\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(14),
      O => \Ysum__1_i_24_n_0\
    );
\Ysum__1_i_25\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(13),
      O => \Ysum__1_i_25_n_0\
    );
\Ysum__1_i_26\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(12),
      O => \Ysum__1_i_26_n_0\
    );
\Ysum__1_i_27\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(11),
      O => \Ysum__1_i_27_n_0\
    );
\Ysum__1_i_28\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(10),
      O => \Ysum__1_i_28_n_0\
    );
\Ysum__1_i_29\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(9),
      O => \Ysum__1_i_29_n_0\
    );
\Ysum__1_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_4_n_0\,
      CO(3) => \Ysum__1_i_3_n_0\,
      CO(2) => \Ysum__1_i_3_n_1\,
      CO(1) => \Ysum__1_i_3_n_2\,
      CO(0) => \Ysum__1_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(11 downto 8),
      S(3) => \Ysum__1_i_27_n_0\,
      S(2) => \Ysum__1_i_28_n_0\,
      S(1) => \Ysum__1_i_29_n_0\,
      S(0) => \Ysum__1_i_30_n_0\
    );
\Ysum__1_i_30\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(8),
      O => \Ysum__1_i_30_n_0\
    );
\Ysum__1_i_31\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(7),
      O => \Ysum__1_i_31_n_0\
    );
\Ysum__1_i_32\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(6),
      O => \Ysum__1_i_32_n_0\
    );
\Ysum__1_i_33\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(5),
      O => \Ysum__1_i_33_n_0\
    );
\Ysum__1_i_34\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(4),
      O => \Ysum__1_i_34_n_0\
    );
\Ysum__1_i_35\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(3),
      O => \Ysum__1_i_35_n_0\
    );
\Ysum__1_i_36\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(2),
      O => \Ysum__1_i_36_n_0\
    );
\Ysum__1_i_37\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(1),
      O => \Ysum__1_i_37_n_0\
    );
\Ysum__1_i_38\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(32),
      O => \Ysum__1_i_38_n_0\
    );
\Ysum__1_i_39\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(31),
      O => \Ysum__1_i_39_n_0\
    );
\Ysum__1_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_5_n_0\,
      CO(3) => \Ysum__1_i_4_n_0\,
      CO(2) => \Ysum__1_i_4_n_1\,
      CO(1) => \Ysum__1_i_4_n_2\,
      CO(0) => \Ysum__1_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(7 downto 4),
      S(3) => \Ysum__1_i_31_n_0\,
      S(2) => \Ysum__1_i_32_n_0\,
      S(1) => \Ysum__1_i_33_n_0\,
      S(0) => \Ysum__1_i_34_n_0\
    );
\Ysum__1_i_40\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(30),
      O => \Ysum__1_i_40_n_0\
    );
\Ysum__1_i_41\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(29),
      O => \Ysum__1_i_41_n_0\
    );
\Ysum__1_i_42\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(28),
      O => \Ysum__1_i_42_n_0\
    );
\Ysum__1_i_43\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(27),
      O => \Ysum__1_i_43_n_0\
    );
\Ysum__1_i_44\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(26),
      O => \Ysum__1_i_44_n_0\
    );
\Ysum__1_i_45\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(25),
      O => \Ysum__1_i_45_n_0\
    );
\Ysum__1_i_46\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(24),
      O => \Ysum__1_i_46_n_0\
    );
\Ysum__1_i_47\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(23),
      O => \Ysum__1_i_47_n_0\
    );
\Ysum__1_i_48\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(22),
      O => \Ysum__1_i_48_n_0\
    );
\Ysum__1_i_49\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(21),
      O => \Ysum__1_i_49_n_0\
    );
\Ysum__1_i_5\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \Ysum__1_i_5_n_0\,
      CO(2) => \Ysum__1_i_5_n_1\,
      CO(1) => \Ysum__1_i_5_n_2\,
      CO(0) => \Ysum__1_i_5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3 downto 0) => Ysum0(3 downto 0),
      S(3) => \Ysum__1_i_35_n_0\,
      S(2) => \Ysum__1_i_36_n_0\,
      S(1) => \Ysum__1_i_37_n_0\,
      S(0) => \YMult1__0\(0)
    );
\Ysum__1_i_50\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(20),
      O => \Ysum__1_i_50_n_0\
    );
\Ysum__1_i_51\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_73,
      O => \Ysum__1_i_51_n_0\
    );
\Ysum__1_i_52\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_74,
      O => \Ysum__1_i_52_n_0\
    );
\Ysum__1_i_53\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_75,
      O => \Ysum__1_i_53_n_0\
    );
\Ysum__1_i_54\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_76,
      O => \Ysum__1_i_54_n_0\
    );
\Ysum__1_i_55\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_77,
      O => \Ysum__1_i_55_n_0\
    );
\Ysum__1_i_56\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_78,
      O => \Ysum__1_i_56_n_0\
    );
\Ysum__1_i_57\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_79,
      O => \Ysum__1_i_57_n_0\
    );
\Ysum__1_i_58\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_80,
      O => \Ysum__1_i_58_n_0\
    );
\Ysum__1_i_59\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_81,
      O => \Ysum__1_i_59_n_0\
    );
\Ysum__1_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_7_n_0\,
      CO(3 downto 0) => \NLW_Ysum__1_i_6_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_Ysum__1_i_6_O_UNCONNECTED\(3 downto 1),
      O(0) => Ysum0(32),
      S(3 downto 1) => B"000",
      S(0) => \Ysum__1_i_38_n_0\
    );
\Ysum__1_i_60\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_82,
      O => \Ysum__1_i_60_n_0\
    );
\Ysum__1_i_61\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_83,
      O => \Ysum__1_i_61_n_0\
    );
\Ysum__1_i_62\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_84,
      O => \Ysum__1_i_62_n_0\
    );
\Ysum__1_i_63\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_85,
      O => \Ysum__1_i_63_n_0\
    );
\Ysum__1_i_64\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_86,
      O => \Ysum__1_i_64_n_0\
    );
\Ysum__1_i_65\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_87,
      O => \Ysum__1_i_65_n_0\
    );
\Ysum__1_i_66\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_88,
      O => \Ysum__1_i_66_n_0\
    );
\Ysum__1_i_67\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_89,
      O => \Ysum__1_i_67_n_0\
    );
\Ysum__1_i_68\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_90,
      O => \Ysum__1_i_68_n_0\
    );
\Ysum__1_i_69\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_91,
      O => \Ysum__1_i_69_n_0\
    );
\Ysum__1_i_7\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_8_n_0\,
      CO(3) => \Ysum__1_i_7_n_0\,
      CO(2) => \Ysum__1_i_7_n_1\,
      CO(1) => \Ysum__1_i_7_n_2\,
      CO(0) => \Ysum__1_i_7_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(31 downto 28),
      S(3) => \Ysum__1_i_39_n_0\,
      S(2) => \Ysum__1_i_40_n_0\,
      S(1) => \Ysum__1_i_41_n_0\,
      S(0) => \Ysum__1_i_42_n_0\
    );
\Ysum__1_i_70\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_92,
      O => \Ysum__1_i_70_n_0\
    );
\Ysum__1_i_71\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_93,
      O => \Ysum__1_i_71_n_0\
    );
\Ysum__1_i_72\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_94,
      O => \Ysum__1_i_72_n_0\
    );
\Ysum__1_i_73\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_95,
      O => \Ysum__1_i_73_n_0\
    );
\Ysum__1_i_74\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_96,
      O => \Ysum__1_i_74_n_0\
    );
\Ysum__1_i_75\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_97,
      O => \Ysum__1_i_75_n_0\
    );
\Ysum__1_i_76\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_98,
      O => \Ysum__1_i_76_n_0\
    );
\Ysum__1_i_77\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_99,
      O => \Ysum__1_i_77_n_0\
    );
\Ysum__1_i_78\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_100,
      O => \Ysum__1_i_78_n_0\
    );
\Ysum__1_i_79\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_101,
      O => \Ysum__1_i_79_n_0\
    );
\Ysum__1_i_8\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_9_n_0\,
      CO(3) => \Ysum__1_i_8_n_0\,
      CO(2) => \Ysum__1_i_8_n_1\,
      CO(1) => \Ysum__1_i_8_n_2\,
      CO(0) => \Ysum__1_i_8_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(27 downto 24),
      S(3) => \Ysum__1_i_43_n_0\,
      S(2) => \Ysum__1_i_44_n_0\,
      S(1) => \Ysum__1_i_45_n_0\,
      S(0) => \Ysum__1_i_46_n_0\
    );
\Ysum__1_i_80\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_102,
      O => \Ysum__1_i_80_n_0\
    );
\Ysum__1_i_81\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_103,
      O => \Ysum__1_i_81_n_0\
    );
\Ysum__1_i_82\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_104,
      O => \Ysum__1_i_82_n_0\
    );
\Ysum__1_i_9\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__1_i_1_n_0\,
      CO(3) => \Ysum__1_i_9_n_0\,
      CO(2) => \Ysum__1_i_9_n_1\,
      CO(1) => \Ysum__1_i_9_n_2\,
      CO(0) => \Ysum__1_i_9_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(23 downto 20),
      S(3) => \Ysum__1_i_47_n_0\,
      S(2) => \Ysum__1_i_48_n_0\,
      S(1) => \Ysum__1_i_49_n_0\,
      S(0) => \Ysum__1_i_50_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ is
  port (
    Xin : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Xin1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Xin2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Yin1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Yin2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Yout : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is "IIR_single_stage_dsp";
  attribute a0 : integer;
  attribute a0 of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is 131072;
  attribute a1 : integer;
  attribute a1 of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is -224081;
  attribute a2 : integer;
  attribute a2 of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is 105456;
  attribute b0 : integer;
  attribute b0 of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is 131072;
  attribute b1 : integer;
  attribute b1 of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is -204435;
  attribute b2 : integer;
  attribute b2 of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is 131072;
  attribute coeffct_width : integer;
  attribute coeffct_width of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is 20;
  attribute daout_width : integer;
  attribute daout_width of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is 16;
  attribute datin_width : integer;
  attribute datin_width of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is 16;
  attribute dont_touch : string;
  attribute dont_touch of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ : entity is "true";
end \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\;

architecture STRUCTURE of \IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\ is
  signal C : STD_LOGIC_VECTOR ( 32 downto 17 );
  signal \YMult1__0\ : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal YMult1_n_71 : STD_LOGIC;
  signal YMult1_n_72 : STD_LOGIC;
  signal YMult2_n_100 : STD_LOGIC;
  signal YMult2_n_101 : STD_LOGIC;
  signal YMult2_n_102 : STD_LOGIC;
  signal YMult2_n_103 : STD_LOGIC;
  signal YMult2_n_104 : STD_LOGIC;
  signal YMult2_n_105 : STD_LOGIC;
  signal YMult2_n_72 : STD_LOGIC;
  signal YMult2_n_73 : STD_LOGIC;
  signal YMult2_n_74 : STD_LOGIC;
  signal YMult2_n_75 : STD_LOGIC;
  signal YMult2_n_76 : STD_LOGIC;
  signal YMult2_n_77 : STD_LOGIC;
  signal YMult2_n_78 : STD_LOGIC;
  signal YMult2_n_79 : STD_LOGIC;
  signal YMult2_n_80 : STD_LOGIC;
  signal YMult2_n_81 : STD_LOGIC;
  signal YMult2_n_82 : STD_LOGIC;
  signal YMult2_n_83 : STD_LOGIC;
  signal YMult2_n_84 : STD_LOGIC;
  signal YMult2_n_85 : STD_LOGIC;
  signal YMult2_n_86 : STD_LOGIC;
  signal YMult2_n_87 : STD_LOGIC;
  signal YMult2_n_88 : STD_LOGIC;
  signal YMult2_n_89 : STD_LOGIC;
  signal YMult2_n_90 : STD_LOGIC;
  signal YMult2_n_91 : STD_LOGIC;
  signal YMult2_n_92 : STD_LOGIC;
  signal YMult2_n_93 : STD_LOGIC;
  signal YMult2_n_94 : STD_LOGIC;
  signal YMult2_n_95 : STD_LOGIC;
  signal YMult2_n_96 : STD_LOGIC;
  signal YMult2_n_97 : STD_LOGIC;
  signal YMult2_n_98 : STD_LOGIC;
  signal YMult2_n_99 : STD_LOGIC;
  signal Ysum0 : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal \Ysum__0_i_11_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_11_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_11_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_11_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_12_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_12_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_12_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_12_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_13_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_13_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_13_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_13_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_14_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_14_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_14_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_14_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_15_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_15_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_15_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_15_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_16_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_16_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_16_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_16_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_17_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_17_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_17_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_17_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_18_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_18_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_18_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_18_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_19_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_1_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_1_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_1_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_1_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_20_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_21_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_22_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_23_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_24_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_25_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_26_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_27_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_28_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_29_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_2_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_2_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_2_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_2_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_30_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_31_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_32_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_33_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_34_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_35_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_36_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_37_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_38_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_39_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_3_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_3_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_3_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_3_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_40_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_41_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_42_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_43_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_44_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_45_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_46_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_47_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_48_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_49_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_4_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_4_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_4_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_4_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_50_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_51_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_52_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_53_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_54_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_55_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_56_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_57_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_58_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_59_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_5_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_5_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_5_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_5_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_60_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_61_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_62_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_63_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_64_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_65_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_66_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_67_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_68_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_69_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_70_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_71_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_72_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_73_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_74_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_75_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_76_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_77_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_78_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_79_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_7_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_7_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_7_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_7_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_80_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_81_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_82_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_8_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_8_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_8_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_8_n_3\ : STD_LOGIC;
  signal \Ysum__0_i_9_n_0\ : STD_LOGIC;
  signal \Ysum__0_i_9_n_1\ : STD_LOGIC;
  signal \Ysum__0_i_9_n_2\ : STD_LOGIC;
  signal \Ysum__0_i_9_n_3\ : STD_LOGIC;
  signal \Ysum__0_n_100\ : STD_LOGIC;
  signal \Ysum__0_n_101\ : STD_LOGIC;
  signal \Ysum__0_n_102\ : STD_LOGIC;
  signal \Ysum__0_n_103\ : STD_LOGIC;
  signal \Ysum__0_n_104\ : STD_LOGIC;
  signal \Ysum__0_n_105\ : STD_LOGIC;
  signal \Ysum__0_n_89\ : STD_LOGIC;
  signal \Ysum__0_n_90\ : STD_LOGIC;
  signal \Ysum__0_n_91\ : STD_LOGIC;
  signal \Ysum__0_n_92\ : STD_LOGIC;
  signal \Ysum__0_n_93\ : STD_LOGIC;
  signal \Ysum__0_n_94\ : STD_LOGIC;
  signal \Ysum__0_n_95\ : STD_LOGIC;
  signal \Ysum__0_n_96\ : STD_LOGIC;
  signal \Ysum__0_n_97\ : STD_LOGIC;
  signal \Ysum__0_n_98\ : STD_LOGIC;
  signal \Ysum__0_n_99\ : STD_LOGIC;
  signal \Ysum__1\ : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal Ysum_i_10_n_0 : STD_LOGIC;
  signal Ysum_i_11_n_0 : STD_LOGIC;
  signal Ysum_i_12_n_0 : STD_LOGIC;
  signal Ysum_i_13_n_0 : STD_LOGIC;
  signal Ysum_i_14_n_0 : STD_LOGIC;
  signal Ysum_i_15_n_0 : STD_LOGIC;
  signal Ysum_i_16_n_0 : STD_LOGIC;
  signal Ysum_i_17_n_0 : STD_LOGIC;
  signal Ysum_i_18_n_0 : STD_LOGIC;
  signal Ysum_i_19_n_0 : STD_LOGIC;
  signal Ysum_i_20_n_0 : STD_LOGIC;
  signal Ysum_i_21_n_0 : STD_LOGIC;
  signal Ysum_i_2_n_0 : STD_LOGIC;
  signal Ysum_i_2_n_1 : STD_LOGIC;
  signal Ysum_i_2_n_2 : STD_LOGIC;
  signal Ysum_i_2_n_3 : STD_LOGIC;
  signal Ysum_i_3_n_0 : STD_LOGIC;
  signal Ysum_i_3_n_1 : STD_LOGIC;
  signal Ysum_i_3_n_2 : STD_LOGIC;
  signal Ysum_i_3_n_3 : STD_LOGIC;
  signal Ysum_i_4_n_0 : STD_LOGIC;
  signal Ysum_i_4_n_1 : STD_LOGIC;
  signal Ysum_i_4_n_2 : STD_LOGIC;
  signal Ysum_i_4_n_3 : STD_LOGIC;
  signal Ysum_i_5_n_0 : STD_LOGIC;
  signal Ysum_i_5_n_1 : STD_LOGIC;
  signal Ysum_i_5_n_2 : STD_LOGIC;
  signal Ysum_i_5_n_3 : STD_LOGIC;
  signal Ysum_i_6_n_0 : STD_LOGIC;
  signal Ysum_i_7_n_0 : STD_LOGIC;
  signal Ysum_i_8_n_0 : STD_LOGIC;
  signal Ysum_i_9_n_0 : STD_LOGIC;
  signal Ysum_n_100 : STD_LOGIC;
  signal Ysum_n_101 : STD_LOGIC;
  signal Ysum_n_102 : STD_LOGIC;
  signal Ysum_n_103 : STD_LOGIC;
  signal Ysum_n_104 : STD_LOGIC;
  signal Ysum_n_105 : STD_LOGIC;
  signal Ysum_n_106 : STD_LOGIC;
  signal Ysum_n_107 : STD_LOGIC;
  signal Ysum_n_108 : STD_LOGIC;
  signal Ysum_n_109 : STD_LOGIC;
  signal Ysum_n_110 : STD_LOGIC;
  signal Ysum_n_111 : STD_LOGIC;
  signal Ysum_n_112 : STD_LOGIC;
  signal Ysum_n_113 : STD_LOGIC;
  signal Ysum_n_114 : STD_LOGIC;
  signal Ysum_n_115 : STD_LOGIC;
  signal Ysum_n_116 : STD_LOGIC;
  signal Ysum_n_117 : STD_LOGIC;
  signal Ysum_n_118 : STD_LOGIC;
  signal Ysum_n_119 : STD_LOGIC;
  signal Ysum_n_120 : STD_LOGIC;
  signal Ysum_n_121 : STD_LOGIC;
  signal Ysum_n_122 : STD_LOGIC;
  signal Ysum_n_123 : STD_LOGIC;
  signal Ysum_n_124 : STD_LOGIC;
  signal Ysum_n_125 : STD_LOGIC;
  signal Ysum_n_126 : STD_LOGIC;
  signal Ysum_n_127 : STD_LOGIC;
  signal Ysum_n_128 : STD_LOGIC;
  signal Ysum_n_129 : STD_LOGIC;
  signal Ysum_n_130 : STD_LOGIC;
  signal Ysum_n_131 : STD_LOGIC;
  signal Ysum_n_132 : STD_LOGIC;
  signal Ysum_n_133 : STD_LOGIC;
  signal Ysum_n_134 : STD_LOGIC;
  signal Ysum_n_135 : STD_LOGIC;
  signal Ysum_n_136 : STD_LOGIC;
  signal Ysum_n_137 : STD_LOGIC;
  signal Ysum_n_138 : STD_LOGIC;
  signal Ysum_n_139 : STD_LOGIC;
  signal Ysum_n_140 : STD_LOGIC;
  signal Ysum_n_141 : STD_LOGIC;
  signal Ysum_n_142 : STD_LOGIC;
  signal Ysum_n_143 : STD_LOGIC;
  signal Ysum_n_144 : STD_LOGIC;
  signal Ysum_n_145 : STD_LOGIC;
  signal Ysum_n_146 : STD_LOGIC;
  signal Ysum_n_147 : STD_LOGIC;
  signal Ysum_n_148 : STD_LOGIC;
  signal Ysum_n_149 : STD_LOGIC;
  signal Ysum_n_150 : STD_LOGIC;
  signal Ysum_n_151 : STD_LOGIC;
  signal Ysum_n_152 : STD_LOGIC;
  signal Ysum_n_153 : STD_LOGIC;
  signal Ysum_n_73 : STD_LOGIC;
  signal Ysum_n_74 : STD_LOGIC;
  signal Ysum_n_75 : STD_LOGIC;
  signal Ysum_n_76 : STD_LOGIC;
  signal Ysum_n_77 : STD_LOGIC;
  signal Ysum_n_78 : STD_LOGIC;
  signal Ysum_n_79 : STD_LOGIC;
  signal Ysum_n_80 : STD_LOGIC;
  signal Ysum_n_81 : STD_LOGIC;
  signal Ysum_n_82 : STD_LOGIC;
  signal Ysum_n_83 : STD_LOGIC;
  signal Ysum_n_84 : STD_LOGIC;
  signal Ysum_n_85 : STD_LOGIC;
  signal Ysum_n_86 : STD_LOGIC;
  signal Ysum_n_87 : STD_LOGIC;
  signal Ysum_n_88 : STD_LOGIC;
  signal Ysum_n_89 : STD_LOGIC;
  signal Ysum_n_90 : STD_LOGIC;
  signal Ysum_n_91 : STD_LOGIC;
  signal Ysum_n_92 : STD_LOGIC;
  signal Ysum_n_93 : STD_LOGIC;
  signal Ysum_n_94 : STD_LOGIC;
  signal Ysum_n_95 : STD_LOGIC;
  signal Ysum_n_96 : STD_LOGIC;
  signal Ysum_n_97 : STD_LOGIC;
  signal Ysum_n_98 : STD_LOGIC;
  signal Ysum_n_99 : STD_LOGIC;
  signal NLW_YMult1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_YMult1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_YMult1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_YMult1_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 35 );
  signal NLW_YMult1_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_YMult2_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_YMult2_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_YMult2_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_YMult2_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_YMult2_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 34 );
  signal NLW_YMult2_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_Ysum_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_Ysum_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_Ysum_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_Ysum_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_Ysum_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 33 );
  signal \NLW_Ysum__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_Ysum__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal \NLW_Ysum__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \NLW_Ysum__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_Ysum__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 33 );
  signal \NLW_Ysum__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \NLW_Ysum__0_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_Ysum__0_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_Ysum__0_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_Ysum__0_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal NLW_Ysum_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_Ysum_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal NLW_Ysum_i_5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of YMult1 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute METHODOLOGY_DRC_VIOS of YMult2 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute METHODOLOGY_DRC_VIOS of Ysum : label is "{SYNTH-13 {cell *THIS*}}";
  attribute METHODOLOGY_DRC_VIOS of \Ysum__0\ : label is "{SYNTH-13 {cell *THIS*}}";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \Ysum__0_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_10\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_11\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_12\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_13\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_14\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_15\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_16\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_17\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_18\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_4\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_5\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_6\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_7\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_8\ : label is 35;
  attribute ADDER_THRESHOLD of \Ysum__0_i_9\ : label is 35;
  attribute ADDER_THRESHOLD of Ysum_i_1 : label is 35;
  attribute ADDER_THRESHOLD of Ysum_i_2 : label is 35;
  attribute ADDER_THRESHOLD of Ysum_i_3 : label is 35;
  attribute ADDER_THRESHOLD of Ysum_i_4 : label is 35;
  attribute ADDER_THRESHOLD of Ysum_i_5 : label is 35;
begin
YMult1: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29 downto 0) => B"111111111111001001010010101111",
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_YMult1_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => Yin1(15),
      B(16) => Yin1(15),
      B(15 downto 0) => Yin1(15 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_YMult1_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_YMult1_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_YMult1_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_YMult1_MULTSIGNOUT_UNCONNECTED,
      OPMODE(6 downto 0) => B"0000101",
      OVERFLOW => NLW_YMult1_OVERFLOW_UNCONNECTED,
      P(47 downto 35) => NLW_YMult1_P_UNCONNECTED(47 downto 35),
      P(34) => YMult1_n_71,
      P(33) => YMult1_n_72,
      P(32 downto 0) => \YMult1__0\(32 downto 0),
      PATTERNBDETECT => NLW_YMult1_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_YMult1_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47 downto 0) => NLW_YMult1_PCOUT_UNCONNECTED(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_YMult1_UNDERFLOW_UNCONNECTED
    );
YMult2: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29) => Yin2(15),
      A(28) => Yin2(15),
      A(27) => Yin2(15),
      A(26) => Yin2(15),
      A(25) => Yin2(15),
      A(24) => Yin2(15),
      A(23) => Yin2(15),
      A(22) => Yin2(15),
      A(21) => Yin2(15),
      A(20) => Yin2(15),
      A(19) => Yin2(15),
      A(18) => Yin2(15),
      A(17) => Yin2(15),
      A(16) => Yin2(15),
      A(15 downto 0) => Yin2(15 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_YMult2_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 0) => B"011001101111110000",
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_YMult2_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_YMult2_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_YMult2_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_YMult2_MULTSIGNOUT_UNCONNECTED,
      OPMODE(6 downto 0) => B"0000101",
      OVERFLOW => NLW_YMult2_OVERFLOW_UNCONNECTED,
      P(47 downto 34) => NLW_YMult2_P_UNCONNECTED(47 downto 34),
      P(33) => YMult2_n_72,
      P(32) => YMult2_n_73,
      P(31) => YMult2_n_74,
      P(30) => YMult2_n_75,
      P(29) => YMult2_n_76,
      P(28) => YMult2_n_77,
      P(27) => YMult2_n_78,
      P(26) => YMult2_n_79,
      P(25) => YMult2_n_80,
      P(24) => YMult2_n_81,
      P(23) => YMult2_n_82,
      P(22) => YMult2_n_83,
      P(21) => YMult2_n_84,
      P(20) => YMult2_n_85,
      P(19) => YMult2_n_86,
      P(18) => YMult2_n_87,
      P(17) => YMult2_n_88,
      P(16) => YMult2_n_89,
      P(15) => YMult2_n_90,
      P(14) => YMult2_n_91,
      P(13) => YMult2_n_92,
      P(12) => YMult2_n_93,
      P(11) => YMult2_n_94,
      P(10) => YMult2_n_95,
      P(9) => YMult2_n_96,
      P(8) => YMult2_n_97,
      P(7) => YMult2_n_98,
      P(6) => YMult2_n_99,
      P(5) => YMult2_n_100,
      P(4) => YMult2_n_101,
      P(3) => YMult2_n_102,
      P(2) => YMult2_n_103,
      P(1) => YMult2_n_104,
      P(0) => YMult2_n_105,
      PATTERNBDETECT => NLW_YMult2_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_YMult2_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47 downto 0) => NLW_YMult2_PCOUT_UNCONNECTED(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_YMult2_UNDERFLOW_UNCONNECTED
    );
Ysum: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 0,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29 downto 0) => B"111111111111001110000101101101",
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_Ysum_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => Xin1(15),
      B(16) => Xin1(15),
      B(15 downto 0) => Xin1(15 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_Ysum_BCOUT_UNCONNECTED(17 downto 0),
      C(47) => C(32),
      C(46) => C(32),
      C(45) => C(32),
      C(44) => C(32),
      C(43) => C(32),
      C(42) => C(32),
      C(41) => C(32),
      C(40) => C(32),
      C(39) => C(32),
      C(38) => C(32),
      C(37) => C(32),
      C(36) => C(32),
      C(35) => C(32),
      C(34) => C(32),
      C(33) => C(32),
      C(32 downto 17) => C(32 downto 17),
      C(16 downto 0) => B"00000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_Ysum_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_Ysum_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_Ysum_MULTSIGNOUT_UNCONNECTED,
      OPMODE(6 downto 0) => B"0110101",
      OVERFLOW => NLW_Ysum_OVERFLOW_UNCONNECTED,
      P(47 downto 33) => NLW_Ysum_P_UNCONNECTED(47 downto 33),
      P(32) => Ysum_n_73,
      P(31) => Ysum_n_74,
      P(30) => Ysum_n_75,
      P(29) => Ysum_n_76,
      P(28) => Ysum_n_77,
      P(27) => Ysum_n_78,
      P(26) => Ysum_n_79,
      P(25) => Ysum_n_80,
      P(24) => Ysum_n_81,
      P(23) => Ysum_n_82,
      P(22) => Ysum_n_83,
      P(21) => Ysum_n_84,
      P(20) => Ysum_n_85,
      P(19) => Ysum_n_86,
      P(18) => Ysum_n_87,
      P(17) => Ysum_n_88,
      P(16) => Ysum_n_89,
      P(15) => Ysum_n_90,
      P(14) => Ysum_n_91,
      P(13) => Ysum_n_92,
      P(12) => Ysum_n_93,
      P(11) => Ysum_n_94,
      P(10) => Ysum_n_95,
      P(9) => Ysum_n_96,
      P(8) => Ysum_n_97,
      P(7) => Ysum_n_98,
      P(6) => Ysum_n_99,
      P(5) => Ysum_n_100,
      P(4) => Ysum_n_101,
      P(3) => Ysum_n_102,
      P(2) => Ysum_n_103,
      P(1) => Ysum_n_104,
      P(0) => Ysum_n_105,
      PATTERNBDETECT => NLW_Ysum_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_Ysum_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47) => Ysum_n_106,
      PCOUT(46) => Ysum_n_107,
      PCOUT(45) => Ysum_n_108,
      PCOUT(44) => Ysum_n_109,
      PCOUT(43) => Ysum_n_110,
      PCOUT(42) => Ysum_n_111,
      PCOUT(41) => Ysum_n_112,
      PCOUT(40) => Ysum_n_113,
      PCOUT(39) => Ysum_n_114,
      PCOUT(38) => Ysum_n_115,
      PCOUT(37) => Ysum_n_116,
      PCOUT(36) => Ysum_n_117,
      PCOUT(35) => Ysum_n_118,
      PCOUT(34) => Ysum_n_119,
      PCOUT(33) => Ysum_n_120,
      PCOUT(32) => Ysum_n_121,
      PCOUT(31) => Ysum_n_122,
      PCOUT(30) => Ysum_n_123,
      PCOUT(29) => Ysum_n_124,
      PCOUT(28) => Ysum_n_125,
      PCOUT(27) => Ysum_n_126,
      PCOUT(26) => Ysum_n_127,
      PCOUT(25) => Ysum_n_128,
      PCOUT(24) => Ysum_n_129,
      PCOUT(23) => Ysum_n_130,
      PCOUT(22) => Ysum_n_131,
      PCOUT(21) => Ysum_n_132,
      PCOUT(20) => Ysum_n_133,
      PCOUT(19) => Ysum_n_134,
      PCOUT(18) => Ysum_n_135,
      PCOUT(17) => Ysum_n_136,
      PCOUT(16) => Ysum_n_137,
      PCOUT(15) => Ysum_n_138,
      PCOUT(14) => Ysum_n_139,
      PCOUT(13) => Ysum_n_140,
      PCOUT(12) => Ysum_n_141,
      PCOUT(11) => Ysum_n_142,
      PCOUT(10) => Ysum_n_143,
      PCOUT(9) => Ysum_n_144,
      PCOUT(8) => Ysum_n_145,
      PCOUT(7) => Ysum_n_146,
      PCOUT(6) => Ysum_n_147,
      PCOUT(5) => Ysum_n_148,
      PCOUT(4) => Ysum_n_149,
      PCOUT(3) => Ysum_n_150,
      PCOUT(2) => Ysum_n_151,
      PCOUT(1) => Ysum_n_152,
      PCOUT(0) => Ysum_n_153,
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_Ysum_UNDERFLOW_UNCONNECTED
    );
\Ysum__0\: unisim.vcomponents.DSP48E1
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 0,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREG => 0,
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_DPORT => false,
      USE_MULT => "NONE",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48"
    )
        port map (
      A(29) => Ysum0(32),
      A(28) => Ysum0(32),
      A(27) => Ysum0(32),
      A(26) => Ysum0(32),
      A(25) => Ysum0(32),
      A(24) => Ysum0(32),
      A(23) => Ysum0(32),
      A(22) => Ysum0(32),
      A(21) => Ysum0(32),
      A(20) => Ysum0(32),
      A(19) => Ysum0(32),
      A(18) => Ysum0(32),
      A(17) => Ysum0(32),
      A(16) => Ysum0(32),
      A(15) => Ysum0(32),
      A(14 downto 0) => Ysum0(32 downto 18),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => \NLW_Ysum__0_ACOUT_UNCONNECTED\(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 0) => Ysum0(17 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => \NLW_Ysum__0_BCOUT_UNCONNECTED\(17 downto 0),
      C(47) => \Ysum__1\(32),
      C(46) => \Ysum__1\(32),
      C(45) => \Ysum__1\(32),
      C(44) => \Ysum__1\(32),
      C(43) => \Ysum__1\(32),
      C(42) => \Ysum__1\(32),
      C(41) => \Ysum__1\(32),
      C(40) => \Ysum__1\(32),
      C(39) => \Ysum__1\(32),
      C(38) => \Ysum__1\(32),
      C(37) => \Ysum__1\(32),
      C(36) => \Ysum__1\(32),
      C(35) => \Ysum__1\(32),
      C(34) => \Ysum__1\(32),
      C(33) => \Ysum__1\(32),
      C(32 downto 0) => \Ysum__1\(32 downto 0),
      CARRYCASCIN => '0',
      CARRYCASCOUT => \NLW_Ysum__0_CARRYCASCOUT_UNCONNECTED\,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => \NLW_Ysum__0_CARRYOUT_UNCONNECTED\(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(24 downto 0) => B"0000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => \NLW_Ysum__0_MULTSIGNOUT_UNCONNECTED\,
      OPMODE(6 downto 0) => B"0011111",
      OVERFLOW => \NLW_Ysum__0_OVERFLOW_UNCONNECTED\,
      P(47 downto 33) => \NLW_Ysum__0_P_UNCONNECTED\(47 downto 33),
      P(32 downto 17) => Yout(15 downto 0),
      P(16) => \Ysum__0_n_89\,
      P(15) => \Ysum__0_n_90\,
      P(14) => \Ysum__0_n_91\,
      P(13) => \Ysum__0_n_92\,
      P(12) => \Ysum__0_n_93\,
      P(11) => \Ysum__0_n_94\,
      P(10) => \Ysum__0_n_95\,
      P(9) => \Ysum__0_n_96\,
      P(8) => \Ysum__0_n_97\,
      P(7) => \Ysum__0_n_98\,
      P(6) => \Ysum__0_n_99\,
      P(5) => \Ysum__0_n_100\,
      P(4) => \Ysum__0_n_101\,
      P(3) => \Ysum__0_n_102\,
      P(2) => \Ysum__0_n_103\,
      P(1) => \Ysum__0_n_104\,
      P(0) => \Ysum__0_n_105\,
      PATTERNBDETECT => \NLW_Ysum__0_PATTERNBDETECT_UNCONNECTED\,
      PATTERNDETECT => \NLW_Ysum__0_PATTERNDETECT_UNCONNECTED\,
      PCIN(47) => Ysum_n_106,
      PCIN(46) => Ysum_n_107,
      PCIN(45) => Ysum_n_108,
      PCIN(44) => Ysum_n_109,
      PCIN(43) => Ysum_n_110,
      PCIN(42) => Ysum_n_111,
      PCIN(41) => Ysum_n_112,
      PCIN(40) => Ysum_n_113,
      PCIN(39) => Ysum_n_114,
      PCIN(38) => Ysum_n_115,
      PCIN(37) => Ysum_n_116,
      PCIN(36) => Ysum_n_117,
      PCIN(35) => Ysum_n_118,
      PCIN(34) => Ysum_n_119,
      PCIN(33) => Ysum_n_120,
      PCIN(32) => Ysum_n_121,
      PCIN(31) => Ysum_n_122,
      PCIN(30) => Ysum_n_123,
      PCIN(29) => Ysum_n_124,
      PCIN(28) => Ysum_n_125,
      PCIN(27) => Ysum_n_126,
      PCIN(26) => Ysum_n_127,
      PCIN(25) => Ysum_n_128,
      PCIN(24) => Ysum_n_129,
      PCIN(23) => Ysum_n_130,
      PCIN(22) => Ysum_n_131,
      PCIN(21) => Ysum_n_132,
      PCIN(20) => Ysum_n_133,
      PCIN(19) => Ysum_n_134,
      PCIN(18) => Ysum_n_135,
      PCIN(17) => Ysum_n_136,
      PCIN(16) => Ysum_n_137,
      PCIN(15) => Ysum_n_138,
      PCIN(14) => Ysum_n_139,
      PCIN(13) => Ysum_n_140,
      PCIN(12) => Ysum_n_141,
      PCIN(11) => Ysum_n_142,
      PCIN(10) => Ysum_n_143,
      PCIN(9) => Ysum_n_144,
      PCIN(8) => Ysum_n_145,
      PCIN(7) => Ysum_n_146,
      PCIN(6) => Ysum_n_147,
      PCIN(5) => Ysum_n_148,
      PCIN(4) => Ysum_n_149,
      PCIN(3) => Ysum_n_150,
      PCIN(2) => Ysum_n_151,
      PCIN(1) => Ysum_n_152,
      PCIN(0) => Ysum_n_153,
      PCOUT(47 downto 0) => \NLW_Ysum__0_PCOUT_UNCONNECTED\(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => \NLW_Ysum__0_UNDERFLOW_UNCONNECTED\
    );
\Ysum__0_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_2_n_0\,
      CO(3) => \Ysum__0_i_1_n_0\,
      CO(2) => \Ysum__0_i_1_n_1\,
      CO(1) => \Ysum__0_i_1_n_2\,
      CO(0) => \Ysum__0_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(19 downto 16),
      S(3) => \Ysum__0_i_19_n_0\,
      S(2) => \Ysum__0_i_20_n_0\,
      S(1) => \Ysum__0_i_21_n_0\,
      S(0) => \Ysum__0_i_22_n_0\
    );
\Ysum__0_i_10\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_11_n_0\,
      CO(3 downto 0) => \NLW_Ysum__0_i_10_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_Ysum__0_i_10_O_UNCONNECTED\(3 downto 1),
      O(0) => \Ysum__1\(32),
      S(3 downto 1) => B"000",
      S(0) => \Ysum__0_i_51_n_0\
    );
\Ysum__0_i_11\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_12_n_0\,
      CO(3) => \Ysum__0_i_11_n_0\,
      CO(2) => \Ysum__0_i_11_n_1\,
      CO(1) => \Ysum__0_i_11_n_2\,
      CO(0) => \Ysum__0_i_11_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__1\(31 downto 28),
      S(3) => \Ysum__0_i_52_n_0\,
      S(2) => \Ysum__0_i_53_n_0\,
      S(1) => \Ysum__0_i_54_n_0\,
      S(0) => \Ysum__0_i_55_n_0\
    );
\Ysum__0_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_13_n_0\,
      CO(3) => \Ysum__0_i_12_n_0\,
      CO(2) => \Ysum__0_i_12_n_1\,
      CO(1) => \Ysum__0_i_12_n_2\,
      CO(0) => \Ysum__0_i_12_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__1\(27 downto 24),
      S(3) => \Ysum__0_i_56_n_0\,
      S(2) => \Ysum__0_i_57_n_0\,
      S(1) => \Ysum__0_i_58_n_0\,
      S(0) => \Ysum__0_i_59_n_0\
    );
\Ysum__0_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_14_n_0\,
      CO(3) => \Ysum__0_i_13_n_0\,
      CO(2) => \Ysum__0_i_13_n_1\,
      CO(1) => \Ysum__0_i_13_n_2\,
      CO(0) => \Ysum__0_i_13_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__1\(23 downto 20),
      S(3) => \Ysum__0_i_60_n_0\,
      S(2) => \Ysum__0_i_61_n_0\,
      S(1) => \Ysum__0_i_62_n_0\,
      S(0) => \Ysum__0_i_63_n_0\
    );
\Ysum__0_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_15_n_0\,
      CO(3) => \Ysum__0_i_14_n_0\,
      CO(2) => \Ysum__0_i_14_n_1\,
      CO(1) => \Ysum__0_i_14_n_2\,
      CO(0) => \Ysum__0_i_14_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__1\(19 downto 16),
      S(3) => \Ysum__0_i_64_n_0\,
      S(2) => \Ysum__0_i_65_n_0\,
      S(1) => \Ysum__0_i_66_n_0\,
      S(0) => \Ysum__0_i_67_n_0\
    );
\Ysum__0_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_16_n_0\,
      CO(3) => \Ysum__0_i_15_n_0\,
      CO(2) => \Ysum__0_i_15_n_1\,
      CO(1) => \Ysum__0_i_15_n_2\,
      CO(0) => \Ysum__0_i_15_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__1\(15 downto 12),
      S(3) => \Ysum__0_i_68_n_0\,
      S(2) => \Ysum__0_i_69_n_0\,
      S(1) => \Ysum__0_i_70_n_0\,
      S(0) => \Ysum__0_i_71_n_0\
    );
\Ysum__0_i_16\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_17_n_0\,
      CO(3) => \Ysum__0_i_16_n_0\,
      CO(2) => \Ysum__0_i_16_n_1\,
      CO(1) => \Ysum__0_i_16_n_2\,
      CO(0) => \Ysum__0_i_16_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__1\(11 downto 8),
      S(3) => \Ysum__0_i_72_n_0\,
      S(2) => \Ysum__0_i_73_n_0\,
      S(1) => \Ysum__0_i_74_n_0\,
      S(0) => \Ysum__0_i_75_n_0\
    );
\Ysum__0_i_17\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_18_n_0\,
      CO(3) => \Ysum__0_i_17_n_0\,
      CO(2) => \Ysum__0_i_17_n_1\,
      CO(1) => \Ysum__0_i_17_n_2\,
      CO(0) => \Ysum__0_i_17_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Ysum__1\(7 downto 4),
      S(3) => \Ysum__0_i_76_n_0\,
      S(2) => \Ysum__0_i_77_n_0\,
      S(1) => \Ysum__0_i_78_n_0\,
      S(0) => \Ysum__0_i_79_n_0\
    );
\Ysum__0_i_18\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \Ysum__0_i_18_n_0\,
      CO(2) => \Ysum__0_i_18_n_1\,
      CO(1) => \Ysum__0_i_18_n_2\,
      CO(0) => \Ysum__0_i_18_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3 downto 0) => \Ysum__1\(3 downto 0),
      S(3) => \Ysum__0_i_80_n_0\,
      S(2) => \Ysum__0_i_81_n_0\,
      S(1) => \Ysum__0_i_82_n_0\,
      S(0) => YMult2_n_105
    );
\Ysum__0_i_19\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(19),
      O => \Ysum__0_i_19_n_0\
    );
\Ysum__0_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_3_n_0\,
      CO(3) => \Ysum__0_i_2_n_0\,
      CO(2) => \Ysum__0_i_2_n_1\,
      CO(1) => \Ysum__0_i_2_n_2\,
      CO(0) => \Ysum__0_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(15 downto 12),
      S(3) => \Ysum__0_i_23_n_0\,
      S(2) => \Ysum__0_i_24_n_0\,
      S(1) => \Ysum__0_i_25_n_0\,
      S(0) => \Ysum__0_i_26_n_0\
    );
\Ysum__0_i_20\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(18),
      O => \Ysum__0_i_20_n_0\
    );
\Ysum__0_i_21\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(17),
      O => \Ysum__0_i_21_n_0\
    );
\Ysum__0_i_22\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(16),
      O => \Ysum__0_i_22_n_0\
    );
\Ysum__0_i_23\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(15),
      O => \Ysum__0_i_23_n_0\
    );
\Ysum__0_i_24\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(14),
      O => \Ysum__0_i_24_n_0\
    );
\Ysum__0_i_25\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(13),
      O => \Ysum__0_i_25_n_0\
    );
\Ysum__0_i_26\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(12),
      O => \Ysum__0_i_26_n_0\
    );
\Ysum__0_i_27\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(11),
      O => \Ysum__0_i_27_n_0\
    );
\Ysum__0_i_28\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(10),
      O => \Ysum__0_i_28_n_0\
    );
\Ysum__0_i_29\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(9),
      O => \Ysum__0_i_29_n_0\
    );
\Ysum__0_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_4_n_0\,
      CO(3) => \Ysum__0_i_3_n_0\,
      CO(2) => \Ysum__0_i_3_n_1\,
      CO(1) => \Ysum__0_i_3_n_2\,
      CO(0) => \Ysum__0_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(11 downto 8),
      S(3) => \Ysum__0_i_27_n_0\,
      S(2) => \Ysum__0_i_28_n_0\,
      S(1) => \Ysum__0_i_29_n_0\,
      S(0) => \Ysum__0_i_30_n_0\
    );
\Ysum__0_i_30\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(8),
      O => \Ysum__0_i_30_n_0\
    );
\Ysum__0_i_31\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(7),
      O => \Ysum__0_i_31_n_0\
    );
\Ysum__0_i_32\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(6),
      O => \Ysum__0_i_32_n_0\
    );
\Ysum__0_i_33\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(5),
      O => \Ysum__0_i_33_n_0\
    );
\Ysum__0_i_34\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(4),
      O => \Ysum__0_i_34_n_0\
    );
\Ysum__0_i_35\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(3),
      O => \Ysum__0_i_35_n_0\
    );
\Ysum__0_i_36\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(2),
      O => \Ysum__0_i_36_n_0\
    );
\Ysum__0_i_37\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(1),
      O => \Ysum__0_i_37_n_0\
    );
\Ysum__0_i_38\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(32),
      O => \Ysum__0_i_38_n_0\
    );
\Ysum__0_i_39\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(31),
      O => \Ysum__0_i_39_n_0\
    );
\Ysum__0_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_5_n_0\,
      CO(3) => \Ysum__0_i_4_n_0\,
      CO(2) => \Ysum__0_i_4_n_1\,
      CO(1) => \Ysum__0_i_4_n_2\,
      CO(0) => \Ysum__0_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(7 downto 4),
      S(3) => \Ysum__0_i_31_n_0\,
      S(2) => \Ysum__0_i_32_n_0\,
      S(1) => \Ysum__0_i_33_n_0\,
      S(0) => \Ysum__0_i_34_n_0\
    );
\Ysum__0_i_40\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(30),
      O => \Ysum__0_i_40_n_0\
    );
\Ysum__0_i_41\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(29),
      O => \Ysum__0_i_41_n_0\
    );
\Ysum__0_i_42\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(28),
      O => \Ysum__0_i_42_n_0\
    );
\Ysum__0_i_43\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(27),
      O => \Ysum__0_i_43_n_0\
    );
\Ysum__0_i_44\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(26),
      O => \Ysum__0_i_44_n_0\
    );
\Ysum__0_i_45\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(25),
      O => \Ysum__0_i_45_n_0\
    );
\Ysum__0_i_46\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(24),
      O => \Ysum__0_i_46_n_0\
    );
\Ysum__0_i_47\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(23),
      O => \Ysum__0_i_47_n_0\
    );
\Ysum__0_i_48\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(22),
      O => \Ysum__0_i_48_n_0\
    );
\Ysum__0_i_49\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(21),
      O => \Ysum__0_i_49_n_0\
    );
\Ysum__0_i_5\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \Ysum__0_i_5_n_0\,
      CO(2) => \Ysum__0_i_5_n_1\,
      CO(1) => \Ysum__0_i_5_n_2\,
      CO(0) => \Ysum__0_i_5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3 downto 0) => Ysum0(3 downto 0),
      S(3) => \Ysum__0_i_35_n_0\,
      S(2) => \Ysum__0_i_36_n_0\,
      S(1) => \Ysum__0_i_37_n_0\,
      S(0) => \YMult1__0\(0)
    );
\Ysum__0_i_50\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \YMult1__0\(20),
      O => \Ysum__0_i_50_n_0\
    );
\Ysum__0_i_51\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_73,
      O => \Ysum__0_i_51_n_0\
    );
\Ysum__0_i_52\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_74,
      O => \Ysum__0_i_52_n_0\
    );
\Ysum__0_i_53\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_75,
      O => \Ysum__0_i_53_n_0\
    );
\Ysum__0_i_54\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_76,
      O => \Ysum__0_i_54_n_0\
    );
\Ysum__0_i_55\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_77,
      O => \Ysum__0_i_55_n_0\
    );
\Ysum__0_i_56\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_78,
      O => \Ysum__0_i_56_n_0\
    );
\Ysum__0_i_57\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_79,
      O => \Ysum__0_i_57_n_0\
    );
\Ysum__0_i_58\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_80,
      O => \Ysum__0_i_58_n_0\
    );
\Ysum__0_i_59\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_81,
      O => \Ysum__0_i_59_n_0\
    );
\Ysum__0_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_7_n_0\,
      CO(3 downto 0) => \NLW_Ysum__0_i_6_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_Ysum__0_i_6_O_UNCONNECTED\(3 downto 1),
      O(0) => Ysum0(32),
      S(3 downto 1) => B"000",
      S(0) => \Ysum__0_i_38_n_0\
    );
\Ysum__0_i_60\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_82,
      O => \Ysum__0_i_60_n_0\
    );
\Ysum__0_i_61\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_83,
      O => \Ysum__0_i_61_n_0\
    );
\Ysum__0_i_62\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_84,
      O => \Ysum__0_i_62_n_0\
    );
\Ysum__0_i_63\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_85,
      O => \Ysum__0_i_63_n_0\
    );
\Ysum__0_i_64\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_86,
      O => \Ysum__0_i_64_n_0\
    );
\Ysum__0_i_65\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_87,
      O => \Ysum__0_i_65_n_0\
    );
\Ysum__0_i_66\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_88,
      O => \Ysum__0_i_66_n_0\
    );
\Ysum__0_i_67\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_89,
      O => \Ysum__0_i_67_n_0\
    );
\Ysum__0_i_68\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_90,
      O => \Ysum__0_i_68_n_0\
    );
\Ysum__0_i_69\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_91,
      O => \Ysum__0_i_69_n_0\
    );
\Ysum__0_i_7\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_8_n_0\,
      CO(3) => \Ysum__0_i_7_n_0\,
      CO(2) => \Ysum__0_i_7_n_1\,
      CO(1) => \Ysum__0_i_7_n_2\,
      CO(0) => \Ysum__0_i_7_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(31 downto 28),
      S(3) => \Ysum__0_i_39_n_0\,
      S(2) => \Ysum__0_i_40_n_0\,
      S(1) => \Ysum__0_i_41_n_0\,
      S(0) => \Ysum__0_i_42_n_0\
    );
\Ysum__0_i_70\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_92,
      O => \Ysum__0_i_70_n_0\
    );
\Ysum__0_i_71\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_93,
      O => \Ysum__0_i_71_n_0\
    );
\Ysum__0_i_72\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_94,
      O => \Ysum__0_i_72_n_0\
    );
\Ysum__0_i_73\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_95,
      O => \Ysum__0_i_73_n_0\
    );
\Ysum__0_i_74\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_96,
      O => \Ysum__0_i_74_n_0\
    );
\Ysum__0_i_75\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_97,
      O => \Ysum__0_i_75_n_0\
    );
\Ysum__0_i_76\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_98,
      O => \Ysum__0_i_76_n_0\
    );
\Ysum__0_i_77\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_99,
      O => \Ysum__0_i_77_n_0\
    );
\Ysum__0_i_78\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_100,
      O => \Ysum__0_i_78_n_0\
    );
\Ysum__0_i_79\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_101,
      O => \Ysum__0_i_79_n_0\
    );
\Ysum__0_i_8\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_9_n_0\,
      CO(3) => \Ysum__0_i_8_n_0\,
      CO(2) => \Ysum__0_i_8_n_1\,
      CO(1) => \Ysum__0_i_8_n_2\,
      CO(0) => \Ysum__0_i_8_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(27 downto 24),
      S(3) => \Ysum__0_i_43_n_0\,
      S(2) => \Ysum__0_i_44_n_0\,
      S(1) => \Ysum__0_i_45_n_0\,
      S(0) => \Ysum__0_i_46_n_0\
    );
\Ysum__0_i_80\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_102,
      O => \Ysum__0_i_80_n_0\
    );
\Ysum__0_i_81\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_103,
      O => \Ysum__0_i_81_n_0\
    );
\Ysum__0_i_82\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => YMult2_n_104,
      O => \Ysum__0_i_82_n_0\
    );
\Ysum__0_i_9\: unisim.vcomponents.CARRY4
     port map (
      CI => \Ysum__0_i_1_n_0\,
      CO(3) => \Ysum__0_i_9_n_0\,
      CO(2) => \Ysum__0_i_9_n_1\,
      CO(1) => \Ysum__0_i_9_n_2\,
      CO(0) => \Ysum__0_i_9_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => Ysum0(23 downto 20),
      S(3) => \Ysum__0_i_47_n_0\,
      S(2) => \Ysum__0_i_48_n_0\,
      S(1) => \Ysum__0_i_49_n_0\,
      S(0) => \Ysum__0_i_50_n_0\
    );
Ysum_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => Ysum_i_2_n_0,
      CO(3 downto 0) => NLW_Ysum_i_1_CO_UNCONNECTED(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => NLW_Ysum_i_1_O_UNCONNECTED(3 downto 1),
      O(0) => C(32),
      S(3 downto 1) => B"000",
      S(0) => Ysum_i_6_n_0
    );
Ysum_i_10: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(11),
      I1 => Xin(11),
      O => Ysum_i_10_n_0
    );
Ysum_i_11: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(10),
      I1 => Xin(10),
      O => Ysum_i_11_n_0
    );
Ysum_i_12: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(9),
      I1 => Xin(9),
      O => Ysum_i_12_n_0
    );
Ysum_i_13: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(8),
      I1 => Xin(8),
      O => Ysum_i_13_n_0
    );
Ysum_i_14: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(7),
      I1 => Xin(7),
      O => Ysum_i_14_n_0
    );
Ysum_i_15: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(6),
      I1 => Xin(6),
      O => Ysum_i_15_n_0
    );
Ysum_i_16: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(5),
      I1 => Xin(5),
      O => Ysum_i_16_n_0
    );
Ysum_i_17: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(4),
      I1 => Xin(4),
      O => Ysum_i_17_n_0
    );
Ysum_i_18: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(3),
      I1 => Xin(3),
      O => Ysum_i_18_n_0
    );
Ysum_i_19: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(2),
      I1 => Xin(2),
      O => Ysum_i_19_n_0
    );
Ysum_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => Ysum_i_3_n_0,
      CO(3) => Ysum_i_2_n_0,
      CO(2) => Ysum_i_2_n_1,
      CO(1) => Ysum_i_2_n_2,
      CO(0) => Ysum_i_2_n_3,
      CYINIT => '0',
      DI(3 downto 0) => Xin2(14 downto 11),
      O(3 downto 0) => C(31 downto 28),
      S(3) => Ysum_i_7_n_0,
      S(2) => Ysum_i_8_n_0,
      S(1) => Ysum_i_9_n_0,
      S(0) => Ysum_i_10_n_0
    );
Ysum_i_20: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(1),
      I1 => Xin(1),
      O => Ysum_i_20_n_0
    );
Ysum_i_21: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(0),
      I1 => Xin(0),
      O => Ysum_i_21_n_0
    );
Ysum_i_3: unisim.vcomponents.CARRY4
     port map (
      CI => Ysum_i_4_n_0,
      CO(3) => Ysum_i_3_n_0,
      CO(2) => Ysum_i_3_n_1,
      CO(1) => Ysum_i_3_n_2,
      CO(0) => Ysum_i_3_n_3,
      CYINIT => '0',
      DI(3 downto 0) => Xin2(10 downto 7),
      O(3 downto 0) => C(27 downto 24),
      S(3) => Ysum_i_11_n_0,
      S(2) => Ysum_i_12_n_0,
      S(1) => Ysum_i_13_n_0,
      S(0) => Ysum_i_14_n_0
    );
Ysum_i_4: unisim.vcomponents.CARRY4
     port map (
      CI => Ysum_i_5_n_0,
      CO(3) => Ysum_i_4_n_0,
      CO(2) => Ysum_i_4_n_1,
      CO(1) => Ysum_i_4_n_2,
      CO(0) => Ysum_i_4_n_3,
      CYINIT => '0',
      DI(3 downto 0) => Xin2(6 downto 3),
      O(3 downto 0) => C(23 downto 20),
      S(3) => Ysum_i_15_n_0,
      S(2) => Ysum_i_16_n_0,
      S(1) => Ysum_i_17_n_0,
      S(0) => Ysum_i_18_n_0
    );
Ysum_i_5: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => Ysum_i_5_n_0,
      CO(2) => Ysum_i_5_n_1,
      CO(1) => Ysum_i_5_n_2,
      CO(0) => Ysum_i_5_n_3,
      CYINIT => '0',
      DI(3 downto 1) => Xin2(2 downto 0),
      DI(0) => '0',
      O(3 downto 1) => C(19 downto 17),
      O(0) => NLW_Ysum_i_5_O_UNCONNECTED(0),
      S(3) => Ysum_i_19_n_0,
      S(2) => Ysum_i_20_n_0,
      S(1) => Ysum_i_21_n_0,
      S(0) => '0'
    );
Ysum_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(15),
      I1 => Xin(15),
      O => Ysum_i_6_n_0
    );
Ysum_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(14),
      I1 => Xin(14),
      O => Ysum_i_7_n_0
    );
Ysum_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(13),
      I1 => Xin(13),
      O => Ysum_i_8_n_0
    );
Ysum_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Xin2(12),
      I1 => Xin(12),
      O => Ysum_i_9_n_0
    );
end STRUCTURE;
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
RSqbsRZSIb+QlYJMfFv1T7uHQ7PiCEXQkl687MHGm2LgPB15GIYcPmqKUSXgtkLsIFes91PTAyyB
9H9cyY4ZUxedcRg/9ZOB5pm3zPqAbcvGPmg1ivMhr/MlS19t5lYKM2tQo+0Yd+arJXlVZu2BMnvn
+I3G9t9tJuWUIWKjI+I=

`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
VRSQ05ZaB6bIhFIQ823mTvlJaG9+5iW5C3+KxGjq0sq9ziCshKOLpOGPDMmOWDqA4uBaxC5IKISr
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PTqGsMrkhv9U0sq+waS0CmwChsk4WB7RspGYUg==

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
tNziOjCznlvIl4dadmB9r23Duf+HQHWOuHmupEU3PJxrazHVtZdNKspG9sRXhF9mjbpnSiKYCdFK
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HrZ09YNFEF6T7DPTZE4=

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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ShfSLoeZeO+Hk5n3xzJRghM0DQ6Sj7NqXFY68w==

`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`protect key_block
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`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 150432)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity IIR_2_core_pipline_0_cache_bram is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 95 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 95 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of IIR_2_core_pipline_0_cache_bram : entity is "cache_bram,blk_mem_gen_v8_4_8,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of IIR_2_core_pipline_0_cache_bram : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of IIR_2_core_pipline_0_cache_bram : entity is "cache_bram";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of IIR_2_core_pipline_0_cache_bram : entity is "blk_mem_gen_v8_4_8,Vivado 2024.1";
end IIR_2_core_pipline_0_cache_bram;

architecture STRUCTURE of IIR_2_core_pipline_0_cache_bram is
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 11;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 11;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "1";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "4";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     18.334476 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "artix7";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "cache_bram.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 1;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 1536;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 1536;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 96;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 96;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 1536;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 1536;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 96;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 96;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "artix7";
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute X_INTERFACE_PARAMETER of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute X_INTERFACE_INFO of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute X_INTERFACE_INFO of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute X_INTERFACE_INFO of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute X_INTERFACE_INFO of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute X_INTERFACE_INFO of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute X_INTERFACE_INFO of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
U0: entity work.IIR_2_core_pipline_0_blk_mem_gen_v8_4_8
     port map (
      addra(10 downto 9) => B"00",
      addra(8 downto 0) => addra(8 downto 0),
      addrb(10 downto 9) => addrb(10 downto 9),
      addrb(8 downto 0) => B"000000000",
      clka => '0',
      clkb => clkb,
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(95 downto 0) => dina(95 downto 0),
      dinb(95 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(95 downto 0) => NLW_U0_douta_UNCONNECTED(95 downto 0),
      doutb(95 downto 0) => doutb(95 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
      s_axi_rdata(95 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(95 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(95 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '0',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity IIR_2_core_pipline_0_IIR_2_core_pipline is
  port (
    clk : in STD_LOGIC;
    rst_n : in STD_LOGIC;
    en_flag : in STD_LOGIC;
    busy : out STD_LOGIC;
    next_en_flag : out STD_LOGIC;
    datin_bram_r_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    datin_bram_r_en : out STD_LOGIC;
    datin_bram_r_addr : out STD_LOGIC_VECTOR ( 11 downto 0 );
    daout_bram_w_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    daout_bram_w_we : out STD_LOGIC;
    daout_bram_w_en : out STD_LOGIC;
    daout_bram_w_addr : out STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute CALC1 : string;
  attribute CALC1 of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is "3'b011";
  attribute CALC2 : string;
  attribute CALC2 of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is "3'b100";
  attribute IDLE : string;
  attribute IDLE of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is "3'b000";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is "IIR_2_core_pipline";
  attribute READ : string;
  attribute READ of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is "3'b001";
  attribute READ_WAIT : string;
  attribute READ_WAIT of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is "3'b010";
  attribute WRITE : string;
  attribute WRITE of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is "3'b101";
  attribute daout_width : integer;
  attribute daout_width of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is 16;
  attribute datin_width : integer;
  attribute datin_width of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is 16;
  attribute dont_touch : string;
  attribute dont_touch of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is "true";
  attribute ds_rate : integer;
  attribute ds_rate of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is 10;
  attribute index_bit : integer;
  attribute index_bit of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is 12;
  attribute index_max : integer;
  attribute index_max of IIR_2_core_pipline_0_IIR_2_core_pipline : entity is 1536;
end IIR_2_core_pipline_0_IIR_2_core_pipline;

architecture STRUCTURE of IIR_2_core_pipline_0_IIR_2_core_pipline is
  signal \<const0>\ : STD_LOGIC;
  signal \FSM_sequential_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_1_n_0\ : STD_LOGIC;
  signal \^busy\ : STD_LOGIC;
  signal busy_i_1_n_0 : STD_LOGIC;
  signal busy_i_2_n_0 : STD_LOGIC;
  signal busy_i_3_n_0 : STD_LOGIC;
  signal busy_i_4_n_0 : STD_LOGIC;
  signal cache_bram_r_data : STD_LOGIC_VECTOR ( 95 downto 0 );
  signal cache_bram_w_data : STD_LOGIC_VECTOR ( 95 downto 0 );
  signal \cache_reg_reg_n_0_[16]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[17]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[18]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[19]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[20]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[21]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[22]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[23]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[24]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[25]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[26]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[27]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[28]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[29]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[30]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[31]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[48]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[49]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[50]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[51]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[52]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[53]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[54]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[55]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[56]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[57]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[58]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[59]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[60]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[61]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[62]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[63]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[80]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[81]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[82]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[83]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[84]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[85]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[86]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[87]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[88]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[89]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[90]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[91]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[92]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[93]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[94]\ : STD_LOGIC;
  signal \cache_reg_reg_n_0_[95]\ : STD_LOGIC;
  signal current_index : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \current_index[10]_i_1_n_0\ : STD_LOGIC;
  signal \current_index[10]_i_3_n_0\ : STD_LOGIC;
  signal \current_index[2]_i_1_n_0\ : STD_LOGIC;
  signal \current_index[3]_i_1_n_0\ : STD_LOGIC;
  signal \current_index[4]_i_1_n_0\ : STD_LOGIC;
  signal \current_index[5]_i_1_n_0\ : STD_LOGIC;
  signal \current_index[6]_i_1_n_0\ : STD_LOGIC;
  signal \current_index[7]_i_1_n_0\ : STD_LOGIC;
  signal \current_index[8]_i_2_n_0\ : STD_LOGIC;
  signal \current_index[9]_i_2_n_0\ : STD_LOGIC;
  signal \^daout_bram_w_data\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^daout_bram_w_we\ : STD_LOGIC;
  signal \^datin_bram_r_addr\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^datin_bram_r_en\ : STD_LOGIC;
  signal \datin_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal ds_counter : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \ds_counter[0]_i_1_n_0\ : STD_LOGIC;
  signal \ds_counter[1]_i_1_n_0\ : STD_LOGIC;
  signal \ds_counter[2]_i_1_n_0\ : STD_LOGIC;
  signal \ds_counter[3]_i_1_n_0\ : STD_LOGIC;
  signal next_en_flag_d : STD_LOGIC;
  signal next_en_flag_d_reg_n_0 : STD_LOGIC;
  signal next_en_flag_r : STD_LOGIC;
  signal next_en_flag_r1_out : STD_LOGIC;
  signal stage1_out : STD_LOGIC;
  signal stage1_result : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal stage2_out : STD_LOGIC;
  signal stage2_result : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal state : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_state[0]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \FSM_sequential_state[2]_i_1\ : label is "soft_lutpair29";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "READ_WAIT:101,CALC1:100,CALC2:011,WRITE:000,IDLE:010,READ:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "READ_WAIT:101,CALC1:100,CALC2:011,WRITE:000,IDLE:010,READ:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[2]\ : label is "READ_WAIT:101,CALC1:100,CALC2:011,WRITE:000,IDLE:010,READ:001";
  attribute SOFT_HLUTNM of busy_i_4 : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \current_index[0]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \current_index[10]_i_2\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \current_index[1]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \current_index[2]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \current_index[3]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \current_index[6]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \current_index[7]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \current_index[9]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \current_index[9]_i_2\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of datin_bram_r_en_INST_0 : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \ds_counter[0]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \ds_counter[1]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \ds_counter[2]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \ds_counter[3]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of next_en_flag_INST_0 : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of next_en_flag_d_i_1 : label is "soft_lutpair37";
  attribute DONT_TOUCH_boolean : boolean;
  attribute DONT_TOUCH_boolean of u_IIR1 : label is std.standard.true;
  attribute a0 : integer;
  attribute a0 of u_IIR1 : label is 131072;
  attribute a1 : integer;
  attribute a1 of u_IIR1 : label is -186275;
  attribute a2 : integer;
  attribute a2 of u_IIR1 : label is 67915;
  attribute b0 : integer;
  attribute b0 of u_IIR1 : label is 1636;
  attribute b1 : integer;
  attribute b1 of u_IIR1 : label is -531;
  attribute b2 : integer;
  attribute b2 of u_IIR1 : label is 1636;
  attribute coeffct_width : integer;
  attribute coeffct_width of u_IIR1 : label is 20;
  attribute daout_width of u_IIR1 : label is 16;
  attribute datin_width of u_IIR1 : label is 16;
  attribute DONT_TOUCH_boolean of u_IIR2 : label is std.standard.true;
  attribute a0 of u_IIR2 : label is 131072;
  attribute a1 of u_IIR2 : label is -224081;
  attribute a2 of u_IIR2 : label is 105456;
  attribute b0 of u_IIR2 : label is 131072;
  attribute b1 of u_IIR2 : label is -204435;
  attribute b2 of u_IIR2 : label is 131072;
  attribute coeffct_width of u_IIR2 : label is 20;
  attribute daout_width of u_IIR2 : label is 16;
  attribute datin_width of u_IIR2 : label is 16;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of u_cache_bram : label is "cache_bram,blk_mem_gen_v8_4_8,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of u_cache_bram : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of u_cache_bram : label is "blk_mem_gen_v8_4_8,Vivado 2024.1";
begin
  busy <= \^busy\;
  daout_bram_w_addr(11) <= \<const0>\;
  daout_bram_w_addr(10 downto 0) <= \^datin_bram_r_addr\(10 downto 0);
  daout_bram_w_data(15 downto 0) <= \^daout_bram_w_data\(15 downto 0);
  daout_bram_w_en <= \^daout_bram_w_we\;
  daout_bram_w_we <= \^daout_bram_w_we\;
  datin_bram_r_addr(11) <= \<const0>\;
  datin_bram_r_addr(10 downto 0) <= \^datin_bram_r_addr\(10 downto 0);
  datin_bram_r_en <= \^datin_bram_r_en\;
\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00C0FF5"
    )
        port map (
      I0 => busy_i_3_n_0,
      I1 => en_flag,
      I2 => state(0),
      I3 => state(2),
      I4 => state(1),
      O => \FSM_sequential_state[0]_i_1_n_0\
    );
\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF030F0A"
    )
        port map (
      I0 => busy_i_3_n_0,
      I1 => en_flag,
      I2 => state(0),
      I3 => state(2),
      I4 => state(1),
      O => \FSM_sequential_state[1]_i_1_n_0\
    );
\FSM_sequential_state[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0CC"
    )
        port map (
      I0 => en_flag,
      I1 => state(0),
      I2 => state(2),
      I3 => state(1),
      O => \FSM_sequential_state[2]_i_1_n_0\
    );
\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => '1',
      CLR => busy_i_2_n_0,
      D => \FSM_sequential_state[0]_i_1_n_0\,
      Q => state(0)
    );
\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => clk,
      CE => '1',
      D => \FSM_sequential_state[1]_i_1_n_0\,
      PRE => busy_i_2_n_0,
      Q => state(1)
    );
\FSM_sequential_state_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => '1',
      CLR => busy_i_2_n_0,
      D => \FSM_sequential_state[2]_i_1_n_0\,
      Q => state(2)
    );
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
busy_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFDD000000C0"
    )
        port map (
      I0 => busy_i_3_n_0,
      I1 => state(1),
      I2 => en_flag,
      I3 => state(2),
      I4 => state(0),
      I5 => \^busy\,
      O => busy_i_1_n_0
    );
busy_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst_n,
      O => busy_i_2_n_0
    );
busy_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"888A"
    )
        port map (
      I0 => \^datin_bram_r_addr\(10),
      I1 => \^datin_bram_r_addr\(9),
      I2 => \current_index[8]_i_2_n_0\,
      I3 => busy_i_4_n_0,
      O => busy_i_3_n_0
    );
busy_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^datin_bram_r_addr\(7),
      I1 => \^datin_bram_r_addr\(6),
      I2 => \^datin_bram_r_addr\(8),
      I3 => \^datin_bram_r_addr\(5),
      O => busy_i_4_n_0
    );
busy_reg: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => '1',
      CLR => busy_i_2_n_0,
      D => busy_i_1_n_0,
      Q => \^busy\
    );
\cache_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(0),
      Q => cache_bram_w_data(16),
      R => '0'
    );
\cache_reg_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(10),
      Q => cache_bram_w_data(26),
      R => '0'
    );
\cache_reg_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(11),
      Q => cache_bram_w_data(27),
      R => '0'
    );
\cache_reg_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(12),
      Q => cache_bram_w_data(28),
      R => '0'
    );
\cache_reg_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(13),
      Q => cache_bram_w_data(29),
      R => '0'
    );
\cache_reg_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(14),
      Q => cache_bram_w_data(30),
      R => '0'
    );
\cache_reg_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(15),
      Q => cache_bram_w_data(31),
      R => '0'
    );
\cache_reg_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(16),
      Q => \cache_reg_reg_n_0_[16]\,
      R => '0'
    );
\cache_reg_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(17),
      Q => \cache_reg_reg_n_0_[17]\,
      R => '0'
    );
\cache_reg_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(18),
      Q => \cache_reg_reg_n_0_[18]\,
      R => '0'
    );
\cache_reg_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(19),
      Q => \cache_reg_reg_n_0_[19]\,
      R => '0'
    );
\cache_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(1),
      Q => cache_bram_w_data(17),
      R => '0'
    );
\cache_reg_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(20),
      Q => \cache_reg_reg_n_0_[20]\,
      R => '0'
    );
\cache_reg_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(21),
      Q => \cache_reg_reg_n_0_[21]\,
      R => '0'
    );
\cache_reg_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(22),
      Q => \cache_reg_reg_n_0_[22]\,
      R => '0'
    );
\cache_reg_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(23),
      Q => \cache_reg_reg_n_0_[23]\,
      R => '0'
    );
\cache_reg_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(24),
      Q => \cache_reg_reg_n_0_[24]\,
      R => '0'
    );
\cache_reg_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(25),
      Q => \cache_reg_reg_n_0_[25]\,
      R => '0'
    );
\cache_reg_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(26),
      Q => \cache_reg_reg_n_0_[26]\,
      R => '0'
    );
\cache_reg_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(27),
      Q => \cache_reg_reg_n_0_[27]\,
      R => '0'
    );
\cache_reg_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(28),
      Q => \cache_reg_reg_n_0_[28]\,
      R => '0'
    );
\cache_reg_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(29),
      Q => \cache_reg_reg_n_0_[29]\,
      R => '0'
    );
\cache_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(2),
      Q => cache_bram_w_data(18),
      R => '0'
    );
\cache_reg_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(30),
      Q => \cache_reg_reg_n_0_[30]\,
      R => '0'
    );
\cache_reg_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(31),
      Q => \cache_reg_reg_n_0_[31]\,
      R => '0'
    );
\cache_reg_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(32),
      Q => cache_bram_w_data(48),
      R => '0'
    );
\cache_reg_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(33),
      Q => cache_bram_w_data(49),
      R => '0'
    );
\cache_reg_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(34),
      Q => cache_bram_w_data(50),
      R => '0'
    );
\cache_reg_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(35),
      Q => cache_bram_w_data(51),
      R => '0'
    );
\cache_reg_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(36),
      Q => cache_bram_w_data(52),
      R => '0'
    );
\cache_reg_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(37),
      Q => cache_bram_w_data(53),
      R => '0'
    );
\cache_reg_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(38),
      Q => cache_bram_w_data(54),
      R => '0'
    );
\cache_reg_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(39),
      Q => cache_bram_w_data(55),
      R => '0'
    );
\cache_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(3),
      Q => cache_bram_w_data(19),
      R => '0'
    );
\cache_reg_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(40),
      Q => cache_bram_w_data(56),
      R => '0'
    );
\cache_reg_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(41),
      Q => cache_bram_w_data(57),
      R => '0'
    );
\cache_reg_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(42),
      Q => cache_bram_w_data(58),
      R => '0'
    );
\cache_reg_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(43),
      Q => cache_bram_w_data(59),
      R => '0'
    );
\cache_reg_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(44),
      Q => cache_bram_w_data(60),
      R => '0'
    );
\cache_reg_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(45),
      Q => cache_bram_w_data(61),
      R => '0'
    );
\cache_reg_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(46),
      Q => cache_bram_w_data(62),
      R => '0'
    );
\cache_reg_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(47),
      Q => cache_bram_w_data(63),
      R => '0'
    );
\cache_reg_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(48),
      Q => \cache_reg_reg_n_0_[48]\,
      R => '0'
    );
\cache_reg_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(49),
      Q => \cache_reg_reg_n_0_[49]\,
      R => '0'
    );
\cache_reg_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(4),
      Q => cache_bram_w_data(20),
      R => '0'
    );
\cache_reg_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(50),
      Q => \cache_reg_reg_n_0_[50]\,
      R => '0'
    );
\cache_reg_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(51),
      Q => \cache_reg_reg_n_0_[51]\,
      R => '0'
    );
\cache_reg_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(52),
      Q => \cache_reg_reg_n_0_[52]\,
      R => '0'
    );
\cache_reg_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(53),
      Q => \cache_reg_reg_n_0_[53]\,
      R => '0'
    );
\cache_reg_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(54),
      Q => \cache_reg_reg_n_0_[54]\,
      R => '0'
    );
\cache_reg_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(55),
      Q => \cache_reg_reg_n_0_[55]\,
      R => '0'
    );
\cache_reg_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(56),
      Q => \cache_reg_reg_n_0_[56]\,
      R => '0'
    );
\cache_reg_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(57),
      Q => \cache_reg_reg_n_0_[57]\,
      R => '0'
    );
\cache_reg_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(58),
      Q => \cache_reg_reg_n_0_[58]\,
      R => '0'
    );
\cache_reg_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(59),
      Q => \cache_reg_reg_n_0_[59]\,
      R => '0'
    );
\cache_reg_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(5),
      Q => cache_bram_w_data(21),
      R => '0'
    );
\cache_reg_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(60),
      Q => \cache_reg_reg_n_0_[60]\,
      R => '0'
    );
\cache_reg_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(61),
      Q => \cache_reg_reg_n_0_[61]\,
      R => '0'
    );
\cache_reg_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(62),
      Q => \cache_reg_reg_n_0_[62]\,
      R => '0'
    );
\cache_reg_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(63),
      Q => \cache_reg_reg_n_0_[63]\,
      R => '0'
    );
\cache_reg_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(64),
      Q => cache_bram_w_data(80),
      R => '0'
    );
\cache_reg_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(65),
      Q => cache_bram_w_data(81),
      R => '0'
    );
\cache_reg_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(66),
      Q => cache_bram_w_data(82),
      R => '0'
    );
\cache_reg_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(67),
      Q => cache_bram_w_data(83),
      R => '0'
    );
\cache_reg_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(68),
      Q => cache_bram_w_data(84),
      R => '0'
    );
\cache_reg_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(69),
      Q => cache_bram_w_data(85),
      R => '0'
    );
\cache_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(6),
      Q => cache_bram_w_data(22),
      R => '0'
    );
\cache_reg_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(70),
      Q => cache_bram_w_data(86),
      R => '0'
    );
\cache_reg_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(71),
      Q => cache_bram_w_data(87),
      R => '0'
    );
\cache_reg_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(72),
      Q => cache_bram_w_data(88),
      R => '0'
    );
\cache_reg_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(73),
      Q => cache_bram_w_data(89),
      R => '0'
    );
\cache_reg_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(74),
      Q => cache_bram_w_data(90),
      R => '0'
    );
\cache_reg_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(75),
      Q => cache_bram_w_data(91),
      R => '0'
    );
\cache_reg_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(76),
      Q => cache_bram_w_data(92),
      R => '0'
    );
\cache_reg_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(77),
      Q => cache_bram_w_data(93),
      R => '0'
    );
\cache_reg_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(78),
      Q => cache_bram_w_data(94),
      R => '0'
    );
\cache_reg_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(79),
      Q => cache_bram_w_data(95),
      R => '0'
    );
\cache_reg_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(7),
      Q => cache_bram_w_data(23),
      R => '0'
    );
\cache_reg_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(80),
      Q => \cache_reg_reg_n_0_[80]\,
      R => '0'
    );
\cache_reg_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(81),
      Q => \cache_reg_reg_n_0_[81]\,
      R => '0'
    );
\cache_reg_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(82),
      Q => \cache_reg_reg_n_0_[82]\,
      R => '0'
    );
\cache_reg_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(83),
      Q => \cache_reg_reg_n_0_[83]\,
      R => '0'
    );
\cache_reg_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(84),
      Q => \cache_reg_reg_n_0_[84]\,
      R => '0'
    );
\cache_reg_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(85),
      Q => \cache_reg_reg_n_0_[85]\,
      R => '0'
    );
\cache_reg_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(86),
      Q => \cache_reg_reg_n_0_[86]\,
      R => '0'
    );
\cache_reg_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(87),
      Q => \cache_reg_reg_n_0_[87]\,
      R => '0'
    );
\cache_reg_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(88),
      Q => \cache_reg_reg_n_0_[88]\,
      R => '0'
    );
\cache_reg_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(89),
      Q => \cache_reg_reg_n_0_[89]\,
      R => '0'
    );
\cache_reg_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(8),
      Q => cache_bram_w_data(24),
      R => '0'
    );
\cache_reg_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(90),
      Q => \cache_reg_reg_n_0_[90]\,
      R => '0'
    );
\cache_reg_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(91),
      Q => \cache_reg_reg_n_0_[91]\,
      R => '0'
    );
\cache_reg_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(92),
      Q => \cache_reg_reg_n_0_[92]\,
      R => '0'
    );
\cache_reg_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(93),
      Q => \cache_reg_reg_n_0_[93]\,
      R => '0'
    );
\cache_reg_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(94),
      Q => \cache_reg_reg_n_0_[94]\,
      R => '0'
    );
\cache_reg_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(95),
      Q => \cache_reg_reg_n_0_[95]\,
      R => '0'
    );
\cache_reg_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => cache_bram_r_data(9),
      Q => cache_bram_w_data(25),
      R => '0'
    );
\current_index[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => state(1),
      I1 => \^datin_bram_r_addr\(0),
      O => current_index(0)
    );
\current_index[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000D1"
    )
        port map (
      I0 => busy_i_3_n_0,
      I1 => state(1),
      I2 => en_flag,
      I3 => state(2),
      I4 => state(0),
      O => \current_index[10]_i_1_n_0\
    );
\current_index[10]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"41"
    )
        port map (
      I0 => state(1),
      I1 => \current_index[10]_i_3_n_0\,
      I2 => \^datin_bram_r_addr\(10),
      O => current_index(10)
    );
\current_index[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^datin_bram_r_addr\(7),
      I1 => \^datin_bram_r_addr\(6),
      I2 => \^datin_bram_r_addr\(8),
      I3 => \^datin_bram_r_addr\(5),
      I4 => \current_index[8]_i_2_n_0\,
      I5 => \^datin_bram_r_addr\(9),
      O => \current_index[10]_i_3_n_0\
    );
\current_index[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \^datin_bram_r_addr\(1),
      I1 => \^datin_bram_r_addr\(0),
      I2 => state(1),
      O => current_index(1)
    );
\current_index[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1540"
    )
        port map (
      I0 => state(1),
      I1 => \^datin_bram_r_addr\(0),
      I2 => \^datin_bram_r_addr\(1),
      I3 => \^datin_bram_r_addr\(2),
      O => \current_index[2]_i_1_n_0\
    );
\current_index[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => state(1),
      I1 => \^datin_bram_r_addr\(1),
      I2 => \^datin_bram_r_addr\(0),
      I3 => \^datin_bram_r_addr\(2),
      I4 => \^datin_bram_r_addr\(3),
      O => \current_index[3]_i_1_n_0\
    );
\current_index[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => state(1),
      I1 => \^datin_bram_r_addr\(2),
      I2 => \^datin_bram_r_addr\(0),
      I3 => \^datin_bram_r_addr\(1),
      I4 => \^datin_bram_r_addr\(3),
      I5 => \^datin_bram_r_addr\(4),
      O => \current_index[4]_i_1_n_0\
    );
\current_index[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"41"
    )
        port map (
      I0 => state(1),
      I1 => \current_index[8]_i_2_n_0\,
      I2 => \^datin_bram_r_addr\(5),
      O => \current_index[5]_i_1_n_0\
    );
\current_index[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4510"
    )
        port map (
      I0 => state(1),
      I1 => \current_index[8]_i_2_n_0\,
      I2 => \^datin_bram_r_addr\(5),
      I3 => \^datin_bram_r_addr\(6),
      O => \current_index[6]_i_1_n_0\
    );
\current_index[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55150040"
    )
        port map (
      I0 => state(1),
      I1 => \^datin_bram_r_addr\(6),
      I2 => \^datin_bram_r_addr\(5),
      I3 => \current_index[8]_i_2_n_0\,
      I4 => \^datin_bram_r_addr\(7),
      O => \current_index[7]_i_1_n_0\
    );
\current_index[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFF4000"
    )
        port map (
      I0 => \current_index[8]_i_2_n_0\,
      I1 => \^datin_bram_r_addr\(5),
      I2 => \^datin_bram_r_addr\(6),
      I3 => \^datin_bram_r_addr\(7),
      I4 => \^datin_bram_r_addr\(8),
      I5 => state(1),
      O => current_index(8)
    );
\current_index[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \^datin_bram_r_addr\(2),
      I1 => \^datin_bram_r_addr\(0),
      I2 => \^datin_bram_r_addr\(1),
      I3 => \^datin_bram_r_addr\(4),
      I4 => \^datin_bram_r_addr\(3),
      O => \current_index[8]_i_2_n_0\
    );
\current_index[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \current_index[9]_i_2_n_0\,
      I1 => \^datin_bram_r_addr\(9),
      I2 => state(1),
      O => current_index(9)
    );
\current_index[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFFFFFF"
    )
        port map (
      I0 => \current_index[8]_i_2_n_0\,
      I1 => \^datin_bram_r_addr\(5),
      I2 => \^datin_bram_r_addr\(8),
      I3 => \^datin_bram_r_addr\(6),
      I4 => \^datin_bram_r_addr\(7),
      O => \current_index[9]_i_2_n_0\
    );
\current_index_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => current_index(0),
      Q => \^datin_bram_r_addr\(0)
    );
\current_index_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => current_index(10),
      Q => \^datin_bram_r_addr\(10)
    );
\current_index_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => current_index(1),
      Q => \^datin_bram_r_addr\(1)
    );
\current_index_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => \current_index[2]_i_1_n_0\,
      Q => \^datin_bram_r_addr\(2)
    );
\current_index_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => \current_index[3]_i_1_n_0\,
      Q => \^datin_bram_r_addr\(3)
    );
\current_index_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => \current_index[4]_i_1_n_0\,
      Q => \^datin_bram_r_addr\(4)
    );
\current_index_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => \current_index[5]_i_1_n_0\,
      Q => \^datin_bram_r_addr\(5)
    );
\current_index_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => \current_index[6]_i_1_n_0\,
      Q => \^datin_bram_r_addr\(6)
    );
\current_index_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => \current_index[7]_i_1_n_0\,
      Q => \^datin_bram_r_addr\(7)
    );
\current_index_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => current_index(8),
      Q => \^datin_bram_r_addr\(8)
    );
\current_index_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => \current_index[10]_i_1_n_0\,
      CLR => busy_i_2_n_0,
      D => current_index(9),
      Q => \^datin_bram_r_addr\(9)
    );
daout_bram_w_en_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => state(1),
      I1 => state(0),
      I2 => state(2),
      O => \^daout_bram_w_we\
    );
datin_bram_r_en_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => state(0),
      I1 => state(2),
      I2 => state(1),
      O => \^datin_bram_r_en\
    );
\datin_reg[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => state(1),
      I1 => state(2),
      I2 => state(0),
      I3 => rst_n,
      O => \datin_reg[15]_i_1_n_0\
    );
\datin_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(0),
      Q => cache_bram_w_data(0),
      R => '0'
    );
\datin_reg_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(10),
      Q => cache_bram_w_data(10),
      R => '0'
    );
\datin_reg_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(11),
      Q => cache_bram_w_data(11),
      R => '0'
    );
\datin_reg_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(12),
      Q => cache_bram_w_data(12),
      R => '0'
    );
\datin_reg_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(13),
      Q => cache_bram_w_data(13),
      R => '0'
    );
\datin_reg_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(14),
      Q => cache_bram_w_data(14),
      R => '0'
    );
\datin_reg_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(15),
      Q => cache_bram_w_data(15),
      R => '0'
    );
\datin_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(1),
      Q => cache_bram_w_data(1),
      R => '0'
    );
\datin_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(2),
      Q => cache_bram_w_data(2),
      R => '0'
    );
\datin_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(3),
      Q => cache_bram_w_data(3),
      R => '0'
    );
\datin_reg_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(4),
      Q => cache_bram_w_data(4),
      R => '0'
    );
\datin_reg_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(5),
      Q => cache_bram_w_data(5),
      R => '0'
    );
\datin_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(6),
      Q => cache_bram_w_data(6),
      R => '0'
    );
\datin_reg_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(7),
      Q => cache_bram_w_data(7),
      R => '0'
    );
\datin_reg_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(8),
      Q => cache_bram_w_data(8),
      R => '0'
    );
\datin_reg_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \datin_reg[15]_i_1_n_0\,
      D => datin_bram_r_data(9),
      Q => cache_bram_w_data(9),
      R => '0'
    );
\ds_counter[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ds_counter(0),
      O => \ds_counter[0]_i_1_n_0\
    );
\ds_counter[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BF0"
    )
        port map (
      I0 => ds_counter(2),
      I1 => ds_counter(3),
      I2 => ds_counter(1),
      I3 => ds_counter(0),
      O => \ds_counter[1]_i_1_n_0\
    );
\ds_counter[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => ds_counter(2),
      I1 => ds_counter(0),
      I2 => ds_counter(1),
      O => \ds_counter[2]_i_1_n_0\
    );
\ds_counter[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7B80"
    )
        port map (
      I0 => ds_counter(1),
      I1 => ds_counter(0),
      I2 => ds_counter(2),
      I3 => ds_counter(3),
      O => \ds_counter[3]_i_1_n_0\
    );
\ds_counter_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => en_flag,
      CLR => busy_i_2_n_0,
      D => \ds_counter[0]_i_1_n_0\,
      Q => ds_counter(0)
    );
\ds_counter_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => en_flag,
      CLR => busy_i_2_n_0,
      D => \ds_counter[1]_i_1_n_0\,
      Q => ds_counter(1)
    );
\ds_counter_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => en_flag,
      CLR => busy_i_2_n_0,
      D => \ds_counter[2]_i_1_n_0\,
      Q => ds_counter(2)
    );
\ds_counter_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => en_flag,
      CLR => busy_i_2_n_0,
      D => \ds_counter[3]_i_1_n_0\,
      Q => ds_counter(3)
    );
next_en_flag_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => next_en_flag_r,
      I1 => next_en_flag_d_reg_n_0,
      O => next_en_flag
    );
next_en_flag_d_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => en_flag,
      I1 => next_en_flag_r,
      O => next_en_flag_d
    );
next_en_flag_d_reg: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => '1',
      CLR => busy_i_2_n_0,
      D => next_en_flag_d,
      Q => next_en_flag_d_reg_n_0
    );
next_en_flag_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02000000"
    )
        port map (
      I0 => en_flag,
      I1 => ds_counter(1),
      I2 => ds_counter(2),
      I3 => ds_counter(0),
      I4 => ds_counter(3),
      O => next_en_flag_r1_out
    );
next_en_flag_r_reg: unisim.vcomponents.FDCE
     port map (
      C => clk,
      CE => '1',
      CLR => busy_i_2_n_0,
      D => next_en_flag_r1_out,
      Q => next_en_flag_r
    );
\stage1_out[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => state(1),
      I1 => state(2),
      I2 => state(0),
      O => stage1_out
    );
\stage1_out_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(0),
      Q => cache_bram_w_data(32),
      R => '0'
    );
\stage1_out_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(10),
      Q => cache_bram_w_data(42),
      R => '0'
    );
\stage1_out_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(11),
      Q => cache_bram_w_data(43),
      R => '0'
    );
\stage1_out_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(12),
      Q => cache_bram_w_data(44),
      R => '0'
    );
\stage1_out_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(13),
      Q => cache_bram_w_data(45),
      R => '0'
    );
\stage1_out_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(14),
      Q => cache_bram_w_data(46),
      R => '0'
    );
\stage1_out_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(15),
      Q => cache_bram_w_data(47),
      R => '0'
    );
\stage1_out_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(1),
      Q => cache_bram_w_data(33),
      R => '0'
    );
\stage1_out_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(2),
      Q => cache_bram_w_data(34),
      R => '0'
    );
\stage1_out_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(3),
      Q => cache_bram_w_data(35),
      R => '0'
    );
\stage1_out_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(4),
      Q => cache_bram_w_data(36),
      R => '0'
    );
\stage1_out_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(5),
      Q => cache_bram_w_data(37),
      R => '0'
    );
\stage1_out_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(6),
      Q => cache_bram_w_data(38),
      R => '0'
    );
\stage1_out_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(7),
      Q => cache_bram_w_data(39),
      R => '0'
    );
\stage1_out_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(8),
      Q => cache_bram_w_data(40),
      R => '0'
    );
\stage1_out_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage1_out,
      D => stage1_result(9),
      Q => cache_bram_w_data(41),
      R => '0'
    );
\stage2_out[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => state(0),
      I1 => state(1),
      I2 => state(2),
      O => stage2_out
    );
\stage2_out_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(0),
      Q => \^daout_bram_w_data\(0),
      R => '0'
    );
\stage2_out_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(10),
      Q => \^daout_bram_w_data\(10),
      R => '0'
    );
\stage2_out_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(11),
      Q => \^daout_bram_w_data\(11),
      R => '0'
    );
\stage2_out_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(12),
      Q => \^daout_bram_w_data\(12),
      R => '0'
    );
\stage2_out_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(13),
      Q => \^daout_bram_w_data\(13),
      R => '0'
    );
\stage2_out_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(14),
      Q => \^daout_bram_w_data\(14),
      R => '0'
    );
\stage2_out_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(15),
      Q => \^daout_bram_w_data\(15),
      R => '0'
    );
\stage2_out_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(1),
      Q => \^daout_bram_w_data\(1),
      R => '0'
    );
\stage2_out_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(2),
      Q => \^daout_bram_w_data\(2),
      R => '0'
    );
\stage2_out_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(3),
      Q => \^daout_bram_w_data\(3),
      R => '0'
    );
\stage2_out_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(4),
      Q => \^daout_bram_w_data\(4),
      R => '0'
    );
\stage2_out_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(5),
      Q => \^daout_bram_w_data\(5),
      R => '0'
    );
\stage2_out_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(6),
      Q => \^daout_bram_w_data\(6),
      R => '0'
    );
\stage2_out_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(7),
      Q => \^daout_bram_w_data\(7),
      R => '0'
    );
\stage2_out_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(8),
      Q => \^daout_bram_w_data\(8),
      R => '0'
    );
\stage2_out_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => stage2_out,
      D => stage2_result(9),
      Q => \^daout_bram_w_data\(9),
      R => '0'
    );
u_IIR1: entity work.IIR_2_core_pipline_0_IIR_single_stage_dsp
     port map (
      Xin(15 downto 0) => cache_bram_w_data(15 downto 0),
      Xin1(15 downto 0) => cache_bram_w_data(31 downto 16),
      Xin2(15) => \cache_reg_reg_n_0_[31]\,
      Xin2(14) => \cache_reg_reg_n_0_[30]\,
      Xin2(13) => \cache_reg_reg_n_0_[29]\,
      Xin2(12) => \cache_reg_reg_n_0_[28]\,
      Xin2(11) => \cache_reg_reg_n_0_[27]\,
      Xin2(10) => \cache_reg_reg_n_0_[26]\,
      Xin2(9) => \cache_reg_reg_n_0_[25]\,
      Xin2(8) => \cache_reg_reg_n_0_[24]\,
      Xin2(7) => \cache_reg_reg_n_0_[23]\,
      Xin2(6) => \cache_reg_reg_n_0_[22]\,
      Xin2(5) => \cache_reg_reg_n_0_[21]\,
      Xin2(4) => \cache_reg_reg_n_0_[20]\,
      Xin2(3) => \cache_reg_reg_n_0_[19]\,
      Xin2(2) => \cache_reg_reg_n_0_[18]\,
      Xin2(1) => \cache_reg_reg_n_0_[17]\,
      Xin2(0) => \cache_reg_reg_n_0_[16]\,
      Yin1(15 downto 0) => cache_bram_w_data(63 downto 48),
      Yin2(15) => \cache_reg_reg_n_0_[63]\,
      Yin2(14) => \cache_reg_reg_n_0_[62]\,
      Yin2(13) => \cache_reg_reg_n_0_[61]\,
      Yin2(12) => \cache_reg_reg_n_0_[60]\,
      Yin2(11) => \cache_reg_reg_n_0_[59]\,
      Yin2(10) => \cache_reg_reg_n_0_[58]\,
      Yin2(9) => \cache_reg_reg_n_0_[57]\,
      Yin2(8) => \cache_reg_reg_n_0_[56]\,
      Yin2(7) => \cache_reg_reg_n_0_[55]\,
      Yin2(6) => \cache_reg_reg_n_0_[54]\,
      Yin2(5) => \cache_reg_reg_n_0_[53]\,
      Yin2(4) => \cache_reg_reg_n_0_[52]\,
      Yin2(3) => \cache_reg_reg_n_0_[51]\,
      Yin2(2) => \cache_reg_reg_n_0_[50]\,
      Yin2(1) => \cache_reg_reg_n_0_[49]\,
      Yin2(0) => \cache_reg_reg_n_0_[48]\,
      Yout(15 downto 0) => stage1_result(15 downto 0)
    );
u_IIR2: entity work.\IIR_2_core_pipline_0_IIR_single_stage_dsp__parameterized0\
     port map (
      Xin(15 downto 0) => cache_bram_w_data(47 downto 32),
      Xin1(15 downto 0) => cache_bram_w_data(63 downto 48),
      Xin2(15) => \cache_reg_reg_n_0_[63]\,
      Xin2(14) => \cache_reg_reg_n_0_[62]\,
      Xin2(13) => \cache_reg_reg_n_0_[61]\,
      Xin2(12) => \cache_reg_reg_n_0_[60]\,
      Xin2(11) => \cache_reg_reg_n_0_[59]\,
      Xin2(10) => \cache_reg_reg_n_0_[58]\,
      Xin2(9) => \cache_reg_reg_n_0_[57]\,
      Xin2(8) => \cache_reg_reg_n_0_[56]\,
      Xin2(7) => \cache_reg_reg_n_0_[55]\,
      Xin2(6) => \cache_reg_reg_n_0_[54]\,
      Xin2(5) => \cache_reg_reg_n_0_[53]\,
      Xin2(4) => \cache_reg_reg_n_0_[52]\,
      Xin2(3) => \cache_reg_reg_n_0_[51]\,
      Xin2(2) => \cache_reg_reg_n_0_[50]\,
      Xin2(1) => \cache_reg_reg_n_0_[49]\,
      Xin2(0) => \cache_reg_reg_n_0_[48]\,
      Yin1(15 downto 0) => cache_bram_w_data(95 downto 80),
      Yin2(15) => \cache_reg_reg_n_0_[95]\,
      Yin2(14) => \cache_reg_reg_n_0_[94]\,
      Yin2(13) => \cache_reg_reg_n_0_[93]\,
      Yin2(12) => \cache_reg_reg_n_0_[92]\,
      Yin2(11) => \cache_reg_reg_n_0_[91]\,
      Yin2(10) => \cache_reg_reg_n_0_[90]\,
      Yin2(9) => \cache_reg_reg_n_0_[89]\,
      Yin2(8) => \cache_reg_reg_n_0_[88]\,
      Yin2(7) => \cache_reg_reg_n_0_[87]\,
      Yin2(6) => \cache_reg_reg_n_0_[86]\,
      Yin2(5) => \cache_reg_reg_n_0_[85]\,
      Yin2(4) => \cache_reg_reg_n_0_[84]\,
      Yin2(3) => \cache_reg_reg_n_0_[83]\,
      Yin2(2) => \cache_reg_reg_n_0_[82]\,
      Yin2(1) => \cache_reg_reg_n_0_[81]\,
      Yin2(0) => \cache_reg_reg_n_0_[80]\,
      Yout(15 downto 0) => stage2_result(15 downto 0)
    );
u_cache_bram: entity work.IIR_2_core_pipline_0_cache_bram
     port map (
      addra(10 downto 9) => B"00",
      addra(8 downto 0) => \^datin_bram_r_addr\(8 downto 0),
      addrb(10 downto 9) => \^datin_bram_r_addr\(10 downto 9),
      addrb(8 downto 0) => B"000000000",
      clka => '0',
      clkb => clk,
      dina(95 downto 80) => cache_bram_w_data(95 downto 80),
      dina(79 downto 64) => \^daout_bram_w_data\(15 downto 0),
      dina(63 downto 0) => cache_bram_w_data(63 downto 0),
      doutb(95 downto 0) => cache_bram_r_data(95 downto 0),
      ena => \^daout_bram_w_we\,
      enb => \^datin_bram_r_en\,
      wea(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity IIR_2_core_pipline_0 is
  port (
    clk : in STD_LOGIC;
    rst_n : in STD_LOGIC;
    en_flag : in STD_LOGIC;
    busy : out STD_LOGIC;
    next_en_flag : out STD_LOGIC;
    datin_bram_r_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    datin_bram_r_en : out STD_LOGIC;
    datin_bram_r_addr : out STD_LOGIC_VECTOR ( 11 downto 0 );
    daout_bram_w_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    daout_bram_w_we : out STD_LOGIC;
    daout_bram_w_en : out STD_LOGIC;
    daout_bram_w_addr : out STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of IIR_2_core_pipline_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of IIR_2_core_pipline_0 : entity is "IIR_2_core_pipline_0,IIR_2_core_pipline,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of IIR_2_core_pipline_0 : entity is "yes";
  attribute IP_DEFINITION_SOURCE : string;
  attribute IP_DEFINITION_SOURCE of IIR_2_core_pipline_0 : entity is "package_project";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of IIR_2_core_pipline_0 : entity is "IIR_2_core_pipline,Vivado 2024.1";
end IIR_2_core_pipline_0;

architecture STRUCTURE of IIR_2_core_pipline_0 is
  attribute CALC1 : string;
  attribute CALC1 of inst : label is "3'b011";
  attribute CALC2 : string;
  attribute CALC2 of inst : label is "3'b100";
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of inst : label is std.standard.true;
  attribute IDLE : string;
  attribute IDLE of inst : label is "3'b000";
  attribute READ : string;
  attribute READ of inst : label is "3'b001";
  attribute READ_WAIT : string;
  attribute READ_WAIT of inst : label is "3'b010";
  attribute WRITE : string;
  attribute WRITE of inst : label is "3'b101";
  attribute daout_width : integer;
  attribute daout_width of inst : label is 16;
  attribute datin_width : integer;
  attribute datin_width of inst : label is 16;
  attribute ds_rate : integer;
  attribute ds_rate of inst : label is 10;
  attribute index_bit : integer;
  attribute index_bit of inst : label is 12;
  attribute index_max : integer;
  attribute index_max of inst : label is 1536;
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of rst_n : signal is "xilinx.com:signal:reset:1.0 rst_n RST";
  attribute X_INTERFACE_PARAMETER of rst_n : signal is "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0";
begin
inst: entity work.IIR_2_core_pipline_0_IIR_2_core_pipline
     port map (
      busy => busy,
      clk => clk,
      daout_bram_w_addr(11 downto 0) => daout_bram_w_addr(11 downto 0),
      daout_bram_w_data(15 downto 0) => daout_bram_w_data(15 downto 0),
      daout_bram_w_en => daout_bram_w_en,
      daout_bram_w_we => daout_bram_w_we,
      datin_bram_r_addr(11 downto 0) => datin_bram_r_addr(11 downto 0),
      datin_bram_r_data(15 downto 0) => datin_bram_r_data(15 downto 0),
      datin_bram_r_en => datin_bram_r_en,
      en_flag => en_flag,
      next_en_flag => next_en_flag,
      rst_n => rst_n
    );
end STRUCTURE;
